Ambit BuildGates Synthesis User Guide

Flow Procedures

Read the Design Data

Listed below are the data formats that Ambit® BuildGates® synthesis accepts as the basic design source. After a generic netlist is generated, Standard Delay Format (SDF) data can also be loaded to include physical design constraints.

■VHDL data

■Verilog data

■Electronic Design Interchange Format — EDIF data

■Ambit Data Base — ADB data

VHDL and Verilog are the typical RTL hardware languages used to design chips. EDIF is primarily used to exchange gate level designs between EDA tools.

ADB data is generated when the do_build_generic command is executed and defines a hierarchical, gate-level netlist which consists of technology-independent ATL (Ambit

Technology Library) and XATL (extended ATL) logic components. The binary .adb file can be saved for reuse with the write_adb command. The ADB file can be used as the source for resynthesis and analysis.

The following paragraphs list the GUI and command line steps to read a Verilog file.

Read Design Data — GUI Procedure

1.Select File – Open – Verilog.

2.Browse for or type-in the path and file name and click Ok.

Read Design Data — Command Line Procedure

Type read_verilog filename.v and press Return.

To load a VHDL, EDIF, or ADB file, use the commands read_vhdl, read_edif, and read_adb, respectively. For syntax detail for each of these commands, refer to the Envisia and Ambit Synthesis Command Reference.

Ambit BuildGates Synthesis User Guide

Flow Procedures

Build Generic Netlist

Below is a flow chart of a typical build task.

Figure 4-2 Typical Build Flow

Read Design Data

Build Generic Netlist

Set Constraints

The following paragraphs list the GUI and command line steps to build a generic netlist.

Build Generic Netlist — GUI Procedure

1.Select Commands – Build Generic.

The Build Generic options form appears.

2.Select one or more options; click Ok.

3.Save the database (in this example, save as an .adb); select File – Save – Ambit database.

4.Browse for or type-in the path, then type-in file name and click Ok.

Ambit BuildGates Synthesis User Guide

Flow Procedures

Build Generic Netlist — Command Line Procedure

1.Type do_build_generic and press Return.

2.To save the complete hierarchical database design as an .adb file, type write_verilog -hierarchical filename.adb and press Return.

3.To specify the top timing module, type set_top_timing_module module_id and press Return.

4.To specify the current module, type set_current_module module_id and press

Return.

Ambit BuildGates Synthesis User Guide

Flow Procedures

Set Constraints

For complete information on the methodology of setting constraints, refer to Setting Timing Constraints in the Envisia Timing Analysis User Guide.

Below is a flow chart of a typical setting constraints task.

Figure 4-3 Typical Timing Constraints Flow

Build Generic Netlist

Set Top/Current

Level Module

Define Ideal Clocks

Optimize

The following paragraphs list the GUI and command line steps to set basic timing constraints.

Set Constraints — GUI Procedure

1.To specify the top timing module, select Modules – with right mouse button, highlight the desired module – release mouse on Set Top Timing Module option. The top timing module is displayed in red letters.

2.To specify the current timing module, select Modules – with right mouse button, highlight the desired module – release mouse on Set Current Module option. The current module is displayed in blue letters.

3.To set ideal clock, select Constraints – press/hold right mouse button in Ideal Clock Panel (see “Constraints Tool” on page 84) – release mouse on New Ideal Clock option.

4.On the Ideal Clock form that is displayed, type the clock name and period; click Ok. By default, the leading edge is set to 0 and the trailing edge is set at the mid-point of the period such that a symmetric clock is generated.

Ambit BuildGates Synthesis User Guide

Flow Procedures

Set Constraints — Command Line Procedure

1.To specify the top timing module, type: set_top_timing_module filename and press Return.

2.To specify the current timing module, type: current_timing_module filename and press Return.

3.To create an ideal clock with a period of 20, type: set_clock i_clk_name -period 20 and press Return.

By default, the leading edge is set to 0 and the trailing edge is set at the mid-point of the period such that a symmetric clock is generated.