- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Using the GUI
Commands Menu Options
Figure 3-13 diagrams the commands menu functions and Table 3-13 defines the options.
Figure 3-13 Commands Menu Function Flow
Main Screen
Main Menu
Commands
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Unload |
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Check |
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DCL Rules |
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Timing |
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Set Target |
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Check |
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Build |
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Technology |
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Netlist |
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Generic |
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Set Operating |
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Load |
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Optimize |
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Parameters |
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DCL Rules |
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Test Rules |
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Table 3-13 Commands Menu Options
Option |
Definition |
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Set Operating |
Specify the voltage, process, and temperature constraints of the |
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Parameters |
design. |
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Voltage |
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range: 0 to 10, default: 5 |
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Process |
– |
for multi-process library, specify the desired process. |
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range: 0 to 10, default: 1 |
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Temperature – specify in Fahrenheit. range: 0o to 200o, default: 25o |
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Set Target |
Specify the target technology as either: |
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Technology |
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■ambit_xatl
■atl
Load DCL Rules |
Load the DCL constraints. For more information refer to Read the |
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Libraries in this book, and Envisia Timing Analysis User Guide |
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“Using Timing Libraries” chapter. |
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Ambit BuildGates Synthesis User Guide |
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Using the GUI |
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Table 3-13 Commands Menu Options, continued |
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Option |
Definition |
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Unload DCL Rules |
Unload the DCL constraints. |
Check Netlist |
Checks structural connectivity of the netlist, including: recursively- |
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defined modules, combinational feedback, undriven nets and pins, |
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multiply-driven nets and pins, and undriven ports. Applies to generic |
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and mapped modules. |
Check Timing |
Performs a variety of consistency and completeness checks on the |
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design’s timing constraints, including: arrival time and required time |
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(external delay) for each clock in a multiple clock system and clock |
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versus data connectivity such as gated clock analysis. Typically |
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used after applying all constraints but before optimizing or report |
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generating. |
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Applies to generic and mapped modules. |
Check Test Rules |
Checks for DFT rule violations, such as gated clocks, derived |
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clocks, and uncontrollable asynchronous signals such as resets. |
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This command operates at the level of the top-DFT module, |
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regardless of the current module. |
Build Generic |
Build the generic netlist. |
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Click any or none of the following options to set the parameters used |
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in the generic build. |
■ Group all processes – create new level of hierarchy based on logic of all processes.
■ Group named processes – create new level of hierarchy based on logic of named processes.
■ Group all subprocesses – create new level of hierarchy based on logic of all subprocesses.
■ Extract FSM – extract FSM for registers marked with state vector directive.
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Using the GUI |
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Table 3-13 Commands Menu Options, continued |
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Option |
Definition |
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Optimize |
To set the logic optimization effort level, choose any one of the |
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following. |
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Low – quickly performs simple mapping steps to meet basic |
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requirements. |
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Medium (default) – searches for alternate mappings and |
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structures to meet all constraints. |
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High – performs detailed algorithms for top optimization. |
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Set the flatten mode, choose any one of the following. |
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On – flatten the logic equations into a sum of products form |
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before applying optimization. |
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Auto – perform limited, non-time-consuming flattening |
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operations. |
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Off (default) |
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Set the priority as one of the following. |
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Area |
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Time (default) |
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Click any or none of the following options to use during |
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optimization. |
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No partition |
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No design rules |
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No area reclaim |
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Minimize area |
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Time budget |
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Incremental |
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Force |
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Checkpoint |
Specify scan file name.
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Ambit BuildGates Synthesis User Guide
Using the GUI
Reports Menu Options
Table 3-14 defines the operations of the icons displayed in the upper right corner of each report screen. For more additional detail and sample reports, refer to Report Generation on page 191.
Table 3-14 Report Icons
Option Description
Generate the report and display it in the report window.
Save the report to a file.
Print the report.
Close the report window.
Figure 3-14 diagrams the reports menu functions and the following sections define the options.
Figure 3-14 Reports Menu Function Flow
Main Screen
Main Menu
Reports
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Hierarchy |
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Design |
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Rules |
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Area |
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End Point |
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Histogram |
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Timing |
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Library |
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Path |
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Histogram |
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Ambit BuildGates Synthesis User Guide
Using the GUI
Timing Report
The timing report provides information concerning the various paths in the design. Table 3-15 defines the timing report options. Timing reports are covered in detail in the Envisia Timing
Analysis User Guide, Generating and Understanding Timing Reports chapter.
Table 3-15 Timing Report Options
Option |
Description |
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all |
This option enables all of the following timing report options. |
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Late mode hold/setup |
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Rise transition |
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Fall transition |
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■ Summary of both rise and fall transitions |
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■ Worst path to each endpoint |
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Mode |
Click either option to enable. |
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Early |
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Late (default) |
Transition |
Click any or none of the following options to enable. |
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Rise transition |
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Fall transition |
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Summary (default) |
Path |
Click either option to enable. |
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Max paths |
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Worst paths |
Number of Paths |
Specify number of paths on which to report. range: 0 to 999,999,999 |
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default: 1 |
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From Pins |
Specify the starting pin in the path. |
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Through Pins |
Specify the through pins in the path. |
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To Pins |
Specify the ending pins in the path. |
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Using the GUI
Area Report
The area report generates a report on the area of the netlist. Table 3-16 defines the area report options.
Table 3-16 |
Area Report Options |
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Description |
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Cells |
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Report on cell area. |
Summary |
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Provide summary report. |
Hierarchical |
Report on structural hierarchy as it exists at various stages in the |
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synthesis process. |
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Library Report
The library report generates a report concerning the technology library used in the design.
Table 3-17 defines the library report options.
Table 3-17 Library Report Options
Option |
Description |
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Cells |
Report information about all cells in the library. |
Wireload model |
Report information on all wireload models in the library. |
Operating |
Report information on all operating conditions in the library. |
conditions |
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Hierarchy Report
The hierarchy report generates a report on the structural hierarchy as it exists at various stages of the synthesis process. Table 3-18 defines the hierarchy report option.
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Using the GUI
Table 3-18 |
Hierarchy Report Option |
Option |
Description |
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Instances |
Report the instance name of the module instantiation in the output. |
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Design Rules Report
The design rules report generates a report on design rule violations. Table 3-19 defines the design rules options.
Table 3-19 Design Rules Report Options
Option |
Description |
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Verbose |
Report all design rules for every net and port in the design even if |
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violations do not exist. |
Hierarchy |
Report the violations for the hierarchal ports. |
Ignore clock |
Do not report the clock net violations. |
Current module |
Report only the violations in the current module. |
only |
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VHDL Library Report
The VHDL library report generates a report on the mappings between all defined VHDL libraries and the directories to which they are mapped. Table 3-20 defines the VHDL library option.
Table 3-20 VHDL Library Report Option
Option Description
Verbose |
Report the contents of the VHDL library. |
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Using the GUI
End Point Slack Histogram Report
The end point histogram report generates a report on the statistical distribution of the timing slack at each point in the design. Figure 3-15 shows a sample histogram and Table 3-15 defines the end point histogram options.
Negative slack values indicate a divergence between the timing constraints and the desired timing result.
Figure 3-15 End Point Slack Histogram Report
number of points in path
double-click on a bar to display a report on pins and instances
end point slack range (in nanoseconds) |
processing status |
The x axis indicates the median slack in nanoseconds; the range is computed automatically. The y axis indicates the number of points in the computation; the range is computed automatically. When you position the cursor over a bar, the total number of points and the minimum and maximum slack time for that bar are displayed.
When you double-click on a bar, a report is displayed. For each pin, the report indicates the following information: status, slack time, arrival time, and required time. For each instance, the report indicates the following information: arc, delay, arrival time, required time and slew.
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Using the GUI
Table 3-21 End Point Slack Histogram Report Options
Option/Icon |
Description |
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Compute Histogram – generate and display the histogram (see |
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Figure 3-15 for a sample histogram). |
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Write Data to a File – a dialog is displayed requesting name and |
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location to save the report file. |
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Print Histogram. |
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Close Window – close the histogram window. |
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all |
Select the ideal clock for which to generate the report. Selecting all |
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generates a report that includes all of the ideal clocks. |
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Maximum count |
Specify the maximum number of points in the computation, |
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default: 100 |
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Mode |
Click either mode option to enable. |
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■ |
Early |
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Late |
Rise |
Report on rise transition. |
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Fall |
Report on fall transition. |
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Path Histogram Report
The path histogram report generates a report on the statistical distribution of the timing path at each point in the design; this histogram helps locate paths that violate timing constraints.
Figure 3-16 shows a sample histogram and Table 3-22 defines the end point histogram options.
Negative slack values indicate a divergence between the timing constraints and the desired timing result.
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Using the GUI
Figure 3-16 Path Histogram Report
double-click on a bar to display a report on pins and instances
number of points in path
timing path slack range (in nanoseconds) |
processing status |
The x axis indicates the median path slack in nanoseconds; the range is computed automatically. The y axis indicates the number of points in the computation; the range is computed automatically. When you position the cursor over a bar, the total number of points and the minimum and maximum path slack time for that bar are displayed.
When you double-click on a bar, a report is displayed. For each pin, the report indicates the following information: status, slack time, arrival time, and required time. For each instance, the report indicates the following information: arc, delay, arrival time, required time and slew.
Table 3-22 Path Histogram Report Options
Option Description
Compute Histogram – generate and display the histogram.
Write Data to a File – a dialog is displayed requesting name and location to save the report file.
Print Histogram.
Close Window – close the histogram window.
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Using the GUI |
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Table 3-22 Path Histogram Report Options, continued |
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Option |
Description |
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all |
Select the ideal clock for which to generate the report. Selecting all |
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generates a report that includes all of the ideal clocks. |
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Maximum Count |
Specify the maximum number of points in the computation, |
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default: 100 |
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Mode |
Click either option to enable. |
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■ |
Early |
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Late |
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Transition |
Click either option to enable. |
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Rise |
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Fall |
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