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Ambit BuildGates Synthesis User Guide

Using the GUI

Commands Menu Options

Figure 3-13 diagrams the commands menu functions and Table 3-13 defines the options.

Figure 3-13 Commands Menu Function Flow

Main Screen

Main Menu

Commands

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Unload

 

 

 

Check

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCL Rules

 

 

 

Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set Target

 

 

 

 

 

 

Check

 

 

 

 

 

 

 

Build

 

 

 

 

Technology

 

 

 

 

 

 

Netlist

 

 

 

 

 

 

 

Generic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set Operating

 

 

 

Load

 

 

 

 

 

 

Check

 

 

 

Optimize

Parameters

 

 

DCL Rules

 

 

 

 

 

 

 

 

 

Test Rules

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3-13 Commands Menu Options

Option

Definition

 

 

 

Set Operating

Specify the voltage, process, and temperature constraints of the

Parameters

design.

 

 

 

Voltage

range: 0 to 10, default: 5

 

Process

for multi-process library, specify the desired process.

 

range: 0 to 10, default: 1

 

Temperature – specify in Fahrenheit. range: 0o to 200o, default: 25o

Set Target

Specify the target technology as either:

Technology

 

 

 

ambit_xatl

atl

Load DCL Rules

Load the DCL constraints. For more information refer to Read the

 

Libraries in this book, and Envisia Timing Analysis User Guide

 

“Using Timing Libraries” chapter.

 

 

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Using the GUI

 

Table 3-13 Commands Menu Options, continued

 

 

Option

Definition

 

 

Unload DCL Rules

Unload the DCL constraints.

Check Netlist

Checks structural connectivity of the netlist, including: recursively-

 

defined modules, combinational feedback, undriven nets and pins,

 

multiply-driven nets and pins, and undriven ports. Applies to generic

 

and mapped modules.

Check Timing

Performs a variety of consistency and completeness checks on the

 

design’s timing constraints, including: arrival time and required time

 

(external delay) for each clock in a multiple clock system and clock

 

versus data connectivity such as gated clock analysis. Typically

 

used after applying all constraints but before optimizing or report

 

generating.

 

Applies to generic and mapped modules.

Check Test Rules

Checks for DFT rule violations, such as gated clocks, derived

 

clocks, and uncontrollable asynchronous signals such as resets.

 

This command operates at the level of the top-DFT module,

 

regardless of the current module.

Build Generic

Build the generic netlist.

 

Click any or none of the following options to set the parameters used

 

in the generic build.

Group all processes – create new level of hierarchy based on logic of all processes.

Group named processes – create new level of hierarchy based on logic of named processes.

Group all subprocesses – create new level of hierarchy based on logic of all subprocesses.

Extract FSM – extract FSM for registers marked with state vector directive.

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Using the GUI

 

Table 3-13 Commands Menu Options, continued

 

 

Option

Definition

 

 

Optimize

To set the logic optimization effort level, choose any one of the

 

following.

 

Low – quickly performs simple mapping steps to meet basic

 

 

requirements.

 

Medium (default) – searches for alternate mappings and

 

 

structures to meet all constraints.

 

High – performs detailed algorithms for top optimization.

 

Set the flatten mode, choose any one of the following.

 

On – flatten the logic equations into a sum of products form

 

 

before applying optimization.

 

Auto – perform limited, non-time-consuming flattening

 

 

operations.

 

 

Off (default)

 

Set the priority as one of the following.

 

 

Area

 

 

Time (default)

 

Click any or none of the following options to use during

 

optimization.

 

 

No partition

 

 

No design rules

 

 

No area reclaim

 

 

Minimize area

 

 

Time budget

 

 

Incremental

 

 

Force

 

 

Checkpoint

Specify scan file name.

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Using the GUI

Reports Menu Options

Table 3-14 defines the operations of the icons displayed in the upper right corner of each report screen. For more additional detail and sample reports, refer to Report Generation on page 191.

Table 3-14 Report Icons

Option Description

Generate the report and display it in the report window.

Save the report to a file.

Print the report.

Close the report window.

Figure 3-14 diagrams the reports menu functions and the following sections define the options.

Figure 3-14 Reports Menu Function Flow

Main Screen

Main Menu

Reports

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hierarchy

 

Design

 

 

 

 

 

 

 

 

 

 

 

Rules

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Area

 

 

 

 

 

 

 

End Point

 

 

 

 

 

 

 

 

 

 

 

Histogram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timing

 

Library

 

VHDL

 

Path

 

 

Library

 

Histogram

 

 

 

 

 

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Using the GUI

Timing Report

The timing report provides information concerning the various paths in the design. Table 3-15 defines the timing report options. Timing reports are covered in detail in the Envisia Timing

Analysis User Guide, Generating and Understanding Timing Reports chapter.

Table 3-15 Timing Report Options

Option

Description

 

 

all

This option enables all of the following timing report options.

 

Late mode hold/setup

 

Rise transition

 

Fall transition

 

Summary of both rise and fall transitions

 

Worst path to each endpoint

Mode

Click either option to enable.

 

Early

 

Late (default)

Transition

Click any or none of the following options to enable.

 

Rise transition

 

Fall transition

 

Summary (default)

Path

Click either option to enable.

 

Max paths

 

Worst paths

Number of Paths

Specify number of paths on which to report. range: 0 to 999,999,999

 

default: 1

From Pins

Specify the starting pin in the path.

Through Pins

Specify the through pins in the path.

To Pins

Specify the ending pins in the path.

 

 

 

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Using the GUI

Area Report

The area report generates a report on the area of the netlist. Table 3-16 defines the area report options.

Table 3-16

Area Report Options

Option

 

Description

 

 

 

Cells

 

Report on cell area.

Summary

 

Provide summary report.

Hierarchical

Report on structural hierarchy as it exists at various stages in the

 

 

synthesis process.

 

 

 

Library Report

The library report generates a report concerning the technology library used in the design.

Table 3-17 defines the library report options.

Table 3-17 Library Report Options

Option

Description

 

 

Cells

Report information about all cells in the library.

Wireload model

Report information on all wireload models in the library.

Operating

Report information on all operating conditions in the library.

conditions

 

 

 

Hierarchy Report

The hierarchy report generates a report on the structural hierarchy as it exists at various stages of the synthesis process. Table 3-18 defines the hierarchy report option.

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Table 3-18

Hierarchy Report Option

Option

Description

 

 

Instances

Report the instance name of the module instantiation in the output.

 

 

Design Rules Report

The design rules report generates a report on design rule violations. Table 3-19 defines the design rules options.

Table 3-19 Design Rules Report Options

Option

Description

 

 

Verbose

Report all design rules for every net and port in the design even if

 

violations do not exist.

Hierarchy

Report the violations for the hierarchal ports.

Ignore clock

Do not report the clock net violations.

Current module

Report only the violations in the current module.

only

 

 

 

VHDL Library Report

The VHDL library report generates a report on the mappings between all defined VHDL libraries and the directories to which they are mapped. Table 3-20 defines the VHDL library option.

Table 3-20 VHDL Library Report Option

Option Description

Verbose

Report the contents of the VHDL library.

 

 

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Using the GUI

End Point Slack Histogram Report

The end point histogram report generates a report on the statistical distribution of the timing slack at each point in the design. Figure 3-15 shows a sample histogram and Table 3-15 defines the end point histogram options.

Negative slack values indicate a divergence between the timing constraints and the desired timing result.

Figure 3-15 End Point Slack Histogram Report

number of points in path

double-click on a bar to display a report on pins and instances

end point slack range (in nanoseconds)

processing status

The x axis indicates the median slack in nanoseconds; the range is computed automatically. The y axis indicates the number of points in the computation; the range is computed automatically. When you position the cursor over a bar, the total number of points and the minimum and maximum slack time for that bar are displayed.

When you double-click on a bar, a report is displayed. For each pin, the report indicates the following information: status, slack time, arrival time, and required time. For each instance, the report indicates the following information: arc, delay, arrival time, required time and slew.

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Using the GUI

Table 3-21 End Point Slack Histogram Report Options

Option/Icon

Description

 

 

 

Compute Histogram – generate and display the histogram (see

 

Figure 3-15 for a sample histogram).

 

Write Data to a File – a dialog is displayed requesting name and

 

location to save the report file.

 

Print Histogram.

 

Close Window – close the histogram window.

all

Select the ideal clock for which to generate the report. Selecting all

 

generates a report that includes all of the ideal clocks.

Maximum count

Specify the maximum number of points in the computation,

 

default: 100

Mode

Click either mode option to enable.

 

Early

 

Late

Rise

Report on rise transition.

Fall

Report on fall transition.

 

 

 

Path Histogram Report

The path histogram report generates a report on the statistical distribution of the timing path at each point in the design; this histogram helps locate paths that violate timing constraints.

Figure 3-16 shows a sample histogram and Table 3-22 defines the end point histogram options.

Negative slack values indicate a divergence between the timing constraints and the desired timing result.

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Using the GUI

Figure 3-16 Path Histogram Report

double-click on a bar to display a report on pins and instances

number of points in path

timing path slack range (in nanoseconds)

processing status

The x axis indicates the median path slack in nanoseconds; the range is computed automatically. The y axis indicates the number of points in the computation; the range is computed automatically. When you position the cursor over a bar, the total number of points and the minimum and maximum path slack time for that bar are displayed.

When you double-click on a bar, a report is displayed. For each pin, the report indicates the following information: status, slack time, arrival time, and required time. For each instance, the report indicates the following information: arc, delay, arrival time, required time and slew.

Table 3-22 Path Histogram Report Options

Option Description

Compute Histogram – generate and display the histogram.

Write Data to a File – a dialog is displayed requesting name and location to save the report file.

Print Histogram.

Close Window – close the histogram window.

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Using the GUI

 

 

 

Table 3-22 Path Histogram Report Options, continued

 

 

 

 

Option

Description

 

 

 

 

all

Select the ideal clock for which to generate the report. Selecting all

 

 

generates a report that includes all of the ideal clocks.

 

Maximum Count

Specify the maximum number of points in the computation,

 

 

default: 100

 

Mode

Click either option to enable.

 

 

Early

 

 

Late

 

Transition

Click either option to enable.

 

 

Rise

 

 

Fall

 

 

 

 

 

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