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ATmega32(L) |
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Electrical Characteristics |
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Absolute Maximum Ratings* |
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Operating Temperature.................................. |
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-55°C to +125°C |
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*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
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Storage Temperature ..................................... |
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-65°C to +150°C |
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age to the device. This is a stress rating only and |
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functional operation of the device at these or |
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Voltage on any Pin except |
RESET |
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other conditions beyond those indicated in the |
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with respect to Ground ................................ |
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-0.5V to VCC+0.5V |
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operational sections of this specification is not |
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Voltage on |
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with respect to Ground |
-0.5V to +13.0V |
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implied. Exposure to absolute maximum rating |
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RESET |
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conditions for extended periods may affect |
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Maximum Operating Voltage |
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6.0V |
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device reliability. |
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DC Current per I/O Pin ............................................... |
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40.0 mA |
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DC Current VCC and GND Pins................................ |
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200.0 mA |
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DC Characteristics |
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TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted) |
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Symbol |
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Parameter |
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Condition |
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Min |
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Typ |
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Max |
Units |
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VIL |
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Input Low Voltage |
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Except XTAL1 pin |
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-0.5 |
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(1) |
V |
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0.2 VCC |
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XTAL1 pin, External |
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(1) |
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VIL1 |
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Input Low Voltage |
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Clock Selected |
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-0.5 |
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0.1 VCC |
V |
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VIH |
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Input High Voltage |
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Except XTAL1 and |
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0.6 VCC |
(2) |
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VCC |
+ 0.5 |
V |
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RESET |
pins |
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VIH1 |
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Input High Voltage |
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XTAL1 pin, External |
0.7 VCC |
(2) |
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VCC |
+ 0.5 |
V |
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Clock Selected |
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(2) |
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VIH2 |
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Input High Voltage |
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RESET pin |
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0.9 VCC |
VCC |
+ 0.5 |
V |
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VOL |
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Output Low Voltage(3) |
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I |
OL |
= 20 mA, V |
CC |
= 5V |
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0.7 |
V |
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(Ports A,B,C,D) |
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IOL = 10 mA, VCC = 3V |
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0.5 |
V |
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VOH |
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Output High Voltage(4) |
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I |
OH |
= -20 mA, V |
CC |
= 5V |
4.0 |
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V |
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(Ports A,B,C,D) |
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IOH = -10 mA, VCC = 3V |
2.2 |
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V |
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IIL |
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Input Leakage |
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VCC = 5.5V, pin low |
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1 |
µA |
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Current I/O Pin |
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(absolute value) |
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IIH |
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Input Leakage |
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VCC = 5.5V, pin high |
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1 |
µA |
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Current I/O Pin |
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(absolute value) |
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RRST |
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Reset Pull-up Resistor |
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30 |
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60 |
kΩ |
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Rpu |
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I/O Pin Pull-up Resistor |
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20 |
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50 |
kΩ |
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285
2503F–AVR–12/03
TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted)
Symbol |
Parameter |
Condition |
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Min |
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Typ |
Max |
Units |
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Active 1 MHz, VCC = 3V |
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1.1 |
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mA |
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(ATmega32L) |
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Active 4 MHz, VCC = 3V |
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3.8 |
5 |
mA |
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(ATmega32L) |
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Active 8 MHz, VCC = 5V |
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12 |
15 |
mA |
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(ATmega32) |
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Power Supply Current |
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ICC |
Idle 1 MHz, VCC |
= 3V |
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0.35 |
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mA |
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(ATmega32L) |
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Idle 4 MHz, VCC |
= 3V |
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1.2 |
2.5 |
mA |
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(ATmega32L) |
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Idle 8 MHz, VCC |
= 5V |
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5.5 |
8 |
mA |
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(ATmega32) |
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Power-down Mode(5) |
WDT enabled, VCC = 3V |
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< 25 |
20 |
µA |
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WDT disabled, VCC = 3V |
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< 1 |
10 |
µA |
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VACIO |
Analog Comparator |
VCC = 5V |
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40 |
mV |
Input Offset Voltage |
Vin = VCC/2 |
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IACLK |
Analog Comparator |
VCC = 5V |
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-50 |
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50 |
nA |
Input Leakage Current |
Vin = VCC/2 |
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tACID |
Analog Comparator |
VCC = 2.7V |
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750 |
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ns |
Propagation Delay |
VCC = 4.0V |
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500 |
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Notes: 1. |
“Max” means the highest value where the pin is guaranteed to be read as low |
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2.“Min” means the lowest value where the pin is guaranteed to be read as high
3.Although each I/O port can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for port A0 - A7, should not exceed 200 mA.
3] The sum of all IOL, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 300 mA. TQFP and MLF Package:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for ports A0 - A7, should not exceed 200 mA. 3] The sum of all IOL, for ports B0 - B4, should not exceed 200 mA.
4] The sum of all IOL, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 200 mA. 5] The sum of all IOL, for ports D3 - D7, should not exceed 200 mA.
6] The sum of all IOL, for ports C0 - C7, should not exceed 200 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
4.Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for port A0 - A7, should not exceed 200 mA.
3] The sum of all IOH, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 300 mA. TQFP and MLF Package:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for ports A0 - A7, should not exceed 200 mA. 3] The sum of all IOH, for ports B0 - B4, should not exceed 200 mA.
4] The sum of all IOH, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 200 mA. 5] The sum of all IOH, for ports D3 - D7, should not exceed 200 mA.
286 ATmega32(L)
2503F–AVR–12/03
ATmega32(L)
6] The sum of all IOH, for ports C0 - C7, should not exceed 200 mA.If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
5. Minimum VCC for Power-down is 2.5V.
External Clock Drive Figure 144. External Clock Drive Waveforms
Waveforms
VIH1
VIL1
External Clock Drive
Table 118. External Clock Drive
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VCC = 2.7V to 5.5V |
VCC = 4.5V to 5.5V |
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Symbol |
Parameter |
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Min |
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Max |
Min |
Max |
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Units |
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1/tCLCL |
Oscillator Frequency |
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0 |
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8 |
0 |
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16 |
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MHz |
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tCLCL |
Clock Period |
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125 |
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62.5 |
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ns |
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tCHCX |
High Time |
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50 |
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25 |
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ns |
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tCLCX |
Low Time |
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50 |
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25 |
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ns |
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tCLCH |
Rise Time |
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1.6 |
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0.5 |
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µs |
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tCHCL |
Fall Time |
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1.6 |
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0.5 |
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µs |
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Change in period from |
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∆ tCLCL |
one clock cycle to the |
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2 |
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2 |
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% |
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next |
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Table 119. External RC Oscillator, Typical Frequencies (VCC = 5V) |
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R [kΩ ](1) |
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C [pF] |
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f(2) |
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100 |
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47 |
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87 kHz |
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33 |
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22 |
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650 kHz |
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10 |
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22 |
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2.0 MHz |
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Notes: 1. |
R should be in the range 3 kΩ |
- 100 kΩ |
, and C should be at least 20 pF. The C values |
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given in the table includes pin capacitance. This will vary with package type. |
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2. The frequency will vary with package type and board layout. |
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287
2503F–AVR–12/03
Two-wire Serial Interface Characteristics
Table 120 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega32 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 145.
Table 120. Two-wire Serial Bus Requirements
Symbol |
Parameter |
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Condition |
Min |
Max |
Units |
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VIL |
Input Low-voltage |
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-0.5 |
0.3 VCC |
V |
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VIH |
Input High-voltage |
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0.7 VCC |
VCC + 0.5 |
V |
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(1) |
Hysteresis of Schmitt Trigger Inputs |
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(2) |
– |
V |
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Vhys |
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0.05 VCC |
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V |
(1) |
Output Low-voltage |
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3 mA sink current |
0 |
0.4 |
V |
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OL |
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tr(1) |
Rise Time for both SDA and SCL |
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20 + 0.1Cb(3)(2) |
300 |
ns |
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t |
of |
(1) |
Output Fall Time from V |
IHmin |
to V |
ILmax |
10 pF < C |
b |
< 400 pF(3) |
20 + 0.1C (3)(2) |
250 |
ns |
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b |
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tSP(1) |
Spikes Suppressed by Input Filter |
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0 |
50(2) |
ns |
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Ii |
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Input Current each I/O Pin |
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0.1VCC < Vi < 0.9VCC |
-10 |
10 |
µA |
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C |
(1) |
Capacitance for each I/O Pin |
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– |
10 |
pF |
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i |
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fSCL |
SCL Clock Frequency |
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fCK(4) > max(16fSCL, 250kHz)(5) |
0 |
400 |
kHz |
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fSCL ≤ |
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100 kHz |
VC C – 0,4V |
1000ns |
Ω |
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---------------------------- |
------------------ |
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Rp |
Value of Pull-up resistor |
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3mA |
Cb |
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fSCL > 100 kHz |
VC C – 0,4V |
300ns |
Ω |
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---------------------------- |
--------------- |
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3mA |
Cb |
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tHD;STA |
Hold Time (repeated) START Condition |
fSCL ≤ |
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100 kHz |
4.0 |
– |
µs |
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fSCL > 100 kHz |
0.6 |
– |
µs |
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tLOW |
Low Period of the SCL Clock |
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fSCL ≤ |
100 kHz(6) |
4.7 |
– |
µs |
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fSCL > 100 kHz(7) |
1.3 |
– |
µs |
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tHIGH |
High period of the SCL clock |
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fSCL ≤ |
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100 kHz |
4.0 |
– |
µs |
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fSCL > 100 kHz |
0.6 |
– |
µs |
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tSU;STA |
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fSCL ≤ |
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100 kHz |
4.7 |
– |
µs |
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Set-up time for a repeated START condition |
fSCL > 100 kHz |
0.6 |
– |
µs |
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tHD;DAT |
Data hold time |
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fSCL ≤ |
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100 kHz |
0 |
3.45 |
µs |
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fSCL > 100 kHz |
0 |
0.9 |
µs |
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tSU;DAT |
Data setup time |
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fSCL ≤ |
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100 kHz |
250 |
– |
ns |
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fSCL > 100 kHz |
100 |
– |
ns |
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tSU;STO |
Setup time for STOP condition |
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fSCL ≤ |
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100 kHz |
4.0 |
– |
µs |
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fSCL > 100 kHz |
0.6 |
– |
µs |
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tBUF |
Bus free time between a STOP and START |
fSCL ≤ |
|
100 kHz |
4.7 |
– |
µs |
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condition |
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fSCL > 100 kHz |
1.3 |
– |
µs |
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Notes: 1. In ATmega32, this parameter is characterized and not 100% tested.
2.Required only for fSCL > 100 kHz.
3.Cb = capacitance of one bus line in pF.
4.fCK = CPU clock frequency
288 ATmega32(L)
2503F–AVR–12/03
ATmega32(L)
Figure 146. SPI Interface Timing Requirements (Master Mode)
SS
6 |
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1 |
SCK |
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(CPOL = 0) |
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2 |
2 |
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SCK |
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(CPOL = 1) |
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4 |
5 |
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3 |
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MISO |
MSB |
... |
LSB |
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(Data Input) |
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7 |
8 |
|
MOSI |
MSB |
... |
LSB |
|
(Data Output) |
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Figure 147. SPI Interface Timing Requirements (Slave Mode)
18 |
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SS |
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9 |
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10 |
16 |
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SCK |
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(CPOL = 0) |
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11 |
11 |
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SCK |
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(CPOL = 1) |
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13 |
14 |
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12 |
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MOSI |
MSB |
... |
LSB |
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(Data Input) |
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15 |
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17 |
|
MISO |
MSB |
... |
LSB |
X |
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(Data Output) |
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290 ATmega32(L)
2503F–AVR–12/03