- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Parity Generator
- •Disabling the Transmitter
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Features
- •Application Section
- •BLS – Boot Loader Section
- •Read-While-Write and no Read-While-Write Flash Sections
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •SPI Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega32 Rev. A
- •Datasheet Change Log for ATmega32
- •Changes from Rev. 2503E-09/03 to Rev. 2503F-12/03
- •Changes from Rev. 2503D-02/03 to Rev. 2503E-09/03
- •Changes from Rev. 2503C-10/02 to Rev. 2503D-02/03
- •Changes from Rev. 2503B-10/02 to Rev. 2503C-10/02
- •Changes from Rev. 2503A-03/02 to Rev. 2503B-10/02
- •Table of Contents
ATmega32(L)
Programming the EEPROM The EEPROM is organized in pages, see Table 112 on page 258. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 260 for details on Command, Address and Data loading):
1.A: Load Command “0001 0001”.
2.G: Load Address High Byte ($00 - $FF)
3.B: Load Address Low Byte ($00 - $FF)
4.C: Load Data ($00 - $FF)
5.E: Latch data (give PAGEL a positive pulse)
K:Repeat 3 through 5 until the entire buffer is filled
L:Program EEPROM page
1.Set BS1 to “0”.
2.Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.
3.Wait until to RDY/BSY goes high before programming the next page. (See Figure 130 for signal waveforms)
Figure 130. Programming the EEPROM Waveforms
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K |
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A |
G |
B |
C |
E |
B |
C |
E |
L |
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DATA |
0x11 |
ADDR. HIGH ADDR. LOW |
DATA |
XX |
ADDR. LOW |
DATA |
XX |
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XA1 |
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XA0 |
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BS1 |
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XTAL1 |
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WR |
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RDY/BSY |
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RESET |
+12V |
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OE |
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PAGEL |
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BS2 |
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Reading the Flash |
The algorithm for reading the Flash memory is as follows (refer to “Programming the |
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Flash” on page 260 for details on Command and Address loading): |
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1.A: Load Command “0000 0010”.
2.G: Load Address High Byte ($00 - $FF)
3.B: Load Address Low Byte ($00 - $FF)
4.Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5.Set BS1 to “1”. The Flash word high byte can now be read at DATA.
263
2503F–AVR–12/03
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6. |
Set OE to “1”. |
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Reading the EEPROM |
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the |
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Flash” on page 260 for details on Command and Address loading): |
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1. |
A: Load Command “0000 0011”. |
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2. |
G: Load Address High Byte ($00 - $FF) |
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3. |
B: Load Address Low Byte ($00 - $FF) |
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Set |
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to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at |
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OE |
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DATA. |
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5. |
Set |
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to “1”. |
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OE |
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Programming the Fuse Low |
The algorithm for programming the Fuse Low bits is as follows (refer to “Programming |
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Bits |
the Flash” on page 260 for details on Command and Data loading): |
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1. |
A: Load Command “0100 0000”. |
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C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. |
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Set BS1 to “0” and BS2 to “0”. |
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4. |
Give |
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to go high. |
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WR |
a negative pulse and wait for RDY/BSY |
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Programming the Fuse High |
The algorithm for programming the Fuse high bits is as follows (refer to “Programming |
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Bits |
the Flash” on page 260 for details on Command and Data loading): |
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1. |
A: Load Command “0100 0000”. |
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C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. |
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Set BS1 to “1” and BS2 to “0”. This selects high data byte. |
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4. |
Give |
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to go high. |
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WR |
a negative pulse and wait for RDY/BSY |
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5. |
Set BS1 to “0”. This selects low data byte. |
Figure 131. Programming the Fuses
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Write Fuse Low byte |
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Write Fuse high byte |
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A |
C |
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A |
C |
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DATA |
$40 |
DATA |
XX |
$40 |
DATA |
XX |
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XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
264 ATmega32(L)
2503F–AVR–12/03
ATmega32(L)
Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 260 for details on Command and Data loading):
1.A: Load Command “0010 0000”.
2.C: Load Data Low Byte. Bit n = “0” programs the Lock bit.
3.Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
Reading the Fuse and Lock |
The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming |
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Bits |
the Flash” on page 260 for details on Command loading): |
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1. |
A: Load Command “0000 0100”. |
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2. |
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to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can |
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OE |
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now be read at DATA (“0” means programmed). |
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3. |
Set |
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to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can |
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OE |
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now be read at DATA (“0” means programmed). |
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4. |
Set |
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to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be |
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OE |
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read at DATA (“0” means programmed). |
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5. |
Set |
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to “1”. |
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OE |
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Figure 132. Mapping between BS1, BS2 and the Fuseand Lock Bits during Read |
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Fuse Low Byte |
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0 |
DATA |
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Lock Bits |
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0 |
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1 |
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BS1 |
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Fuse High Byte |
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1 |
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BS2
Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 260 for details on Command and Address loading):
1.A: Load Command “0000 1000”.
2.B: Load Address Low Byte ($00 - $02).
3.Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4.Set OE to “1”.
Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 260 for details on Command and Address loading):
1.A: Load Command “0000 1000”.
2.B: Load Address Low Byte, $00.
3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4.Set OE to “1”.
265
2503F–AVR–12/03
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Parallel Programming |
Figure 133. Parallel Programming Timing, Including some General Timing |
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Characteristics |
Requirements |
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tXLWL |
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XTAL1 |
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tXHXL |
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Data & Contol |
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tDVXH |
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tXLDX |
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(DATA, XA0/1, BS1, BS2) |
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tBVPH |
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tPLBX |
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t BVWL |
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tWLBX |
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PAGEL |
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tPHPL |
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tWL WH |
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tPLWL |
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WLRL |
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RDY/BSY |
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tWLRH |
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Figure 134 . Parallel Programming Timing, Loading Sequence with Timing |
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Requirements(1) |
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LOAD ADDRESS |
LOAD DATA |
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LOAD DATA LOAD DATA |
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LOAD ADDRESS |
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(LOW BYTE) |
(LOW BYTE) |
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(HIGH BYTE) |
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(LOW BYTE) |
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t XLXH |
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tXLPH |
tPLXH |
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XTAL1 |
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BS1 |
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PAGEL |
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DATA |
ADDR0 (Low Byte) |
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DATA (Low Byte) |
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DATA (High Byte) |
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ADDR1 (Low Byte) |
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XA0 |
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XA1 |
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Note: |
1. The timing requirements shown in Figure 133 (i.e., tDVXH, tXHXL, and tXLDX) also apply |
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to loading operation. |
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266 ATmega32(L)
2503F–AVR–12/03
ATmega32(L)
Figure 135. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)
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LOAD ADDRESS |
READ DATA |
READ DATA |
LOAD ADDRESS |
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(LOW BYTE) |
(LOW BYTE) |
(HIGH BYTE) |
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(LOW BYTE) |
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tXLOL |
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XTAL1 |
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BS1 |
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tBVDV |
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tOLDV |
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tOHDZ |
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ADDR1 (Low Byte) |
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DATA |
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ADDR0 (Low Byte) |
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DATA (Low Byte) |
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XA0 |
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XA1 |
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Note: 1. |
The timing requirements shown in Figure 133 (i.e., tDVXH, tXHXL, and tXLDX) also apply |
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Table 113. |
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Parallel Programming Characteristics, VCC = 5 V ± 10% |
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Parameter |
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Min |
Typ |
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Max |
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Units |
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VPP |
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Programming Enable Voltage |
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11.5 |
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12.5 |
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V |
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IPP |
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Programming Enable Current |
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250 |
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A |
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tDVXH |
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Data and Control Valid before XTAL1 High |
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67 |
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ns |
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tXLXH |
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XTAL1 Low to XTAL1 High |
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200 |
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ns |
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tXHXL |
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XTAL1 Pulse Width High |
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150 |
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ns |
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tXLDX |
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Data and Control Hold after XTAL1 Low |
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67 |
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ns |
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tXLWL |
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XTAL1 Low to |
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Low |
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0 |
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ns |
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tXLPH |
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XTAL1 Low to PAGEL high |
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0 |
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ns |
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tPLXH |
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PAGEL low to XTAL1 high |
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150 |
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ns |
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tBVPH |
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BS1 Valid before PAGEL High |
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67 |
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ns |
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tPHPL |
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PAGEL Pulse Width High |
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150 |
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ns |
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tPLBX |
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BS1 Hold after PAGEL Low |
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67 |
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ns |
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tWLBX |
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BS2/1 Hold after |
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Low |
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67 |
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ns |
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PAGEL Low to |
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Low |
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67 |
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ns |
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tBVWL |
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BS1 Valid to |
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Low |
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67 |
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ns |
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tWLWH |
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Pulse Width Low |
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150 |
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ns |
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WR |
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tWLRL |
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Low |
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0 |
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1 |
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s |
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WR |
Low to RDY/BSY |
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tWLRH |
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High(1) |
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3.7 |
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4.5 |
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ms |
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WR |
Low to RDY/BSY |
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tWLRH_CE |
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High for Chip Erase(2) |
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7.5 |
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9 |
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WR |
Low to RDY/BSY |
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tXLOL |
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XTAL1 Low to |
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Low |
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0 |
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ns |
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OE |
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267
2503F–AVR–12/03