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ATmega32(L)

IEEE 1149.1 (JTAG)

Boundary-scan

Features

JTAG (IEEE std. 1149.1 Compliant) Interface

 

Boundary-scan Capabilities According to the JTAG Standard

 

Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections

 

Supports the Optional IDCODE Instruction

 

Additional Public AVR_RESET Instruction to Reset the AVR

System Overview

The Boundary-scan chain has the capability of driving and observing the logic levels on

 

the digital I/O pins, as well as the boundary between digital and analog logic for analog

 

circuitry having Off-chip connections. At system level, all ICs having JTAG capabilities

 

are connected serially by the TDI/TDO signals to form a long Shift Register. An external

 

controller sets up the devices to drive values at their output pins, and observe the input

 

values received from other devices. The controller compares the received data with the

 

expected result. In this way, Boundary-scan provides a mechanism for testing intercon-

 

nections and integrity of components on Printed Circuits Boards by using the four TAP

 

signals only.

 

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAM-

 

PLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction

 

AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the

 

Data Register path will show the ID-code of the device, since IDCODE is the default

 

JTAG instruction. It may be desirable to have the AVR device in Reset during Test

 

mode. If not reset, inputs to the device may be determined by the scan operations, and

 

the internal software may be in an undetermined state when exiting the Test mode.

 

Entering reset, the outputs of any Port Pin will instantly enter the high impedance state,

 

making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be

 

issued to make the shortest possible scan chain through the device. The device can be

 

set in the reset state either by pulling the external

 

pin low, or issuing the

 

RESET

 

AVR_RESET instruction with appropriate setting of the Reset Data Register.

 

The EXTEST instruction is used for sampling external pins and loading output pins with

 

data. The data from the output latch will be driven out on the pins as soon as the

 

EXTEST instruction is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRE-

 

LOAD should also be used for setting initial values to the scan ring, to avoid damaging

 

the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD

 

can also be used for taking a snapshot of the external pins during normal operation of

 

the part.

 

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSR

 

must be cleared to enable the JTAG Test Access Port.

 

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency

 

higher than the internal chip frequency is possible. The chip clock is not required to run.

Data Registers

The Data Registers relevant for Boundary-scan operations are:

 

Bypass Register

 

Device Identification Register

 

Reset Register

• Boundary-scan Chain

223

2503F–AVR–12/03

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The Bypass Register consists of a single Shift Register stage. When the Bypass Regis-

 

ter is selected as path between TDI and TDO, the register is reset to 0 when leaving the

 

Capture-DR controller state. The Bypass Register can be used to shorten the scan

 

chain on a system when the other devices are to be tested.

 

Device Identification Register Figure 114 shows the structure of the Device Identification Register.

 

 

Figure 114. The Format of the Device Identification Register

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB

 

Bit

31

28

 

 

 

27

12

 

11

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device ID

 

Version

 

 

 

 

Part Number

 

 

Manufacturer ID

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 bits

 

 

 

 

 

 

 

16 bits

 

11 bits

1 bit

 

• Version

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Version is a 4 bit number identifying the revision of the component. The relevant version

 

number is shown in Table 87.

 

 

 

 

 

 

 

 

 

 

 

 

Table 87. JTAG Version Numbers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Version

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Version Number (Hex)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ATmega32 revision A

 

 

 

 

 

 

 

 

 

 

0x0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Part Number

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The part number is a 16-bit code identifying the component. The JTAG Part Number for

 

ATmega32 is listed in Table 88.

 

 

 

 

 

 

 

 

 

 

 

 

Table 88. AVR JTAG Part Number

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Part Number

 

 

 

 

 

 

 

JTAG Part Number (Hex)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ATmega32

 

 

 

 

 

 

 

0x9502

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Manufacturer ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufac-

 

turer ID for ATMEL is listed in Table 89.

 

 

 

 

Table 89.

Manufacturer ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Manufacturer

 

 

 

 

 

 

 

 

 

JTAG Man. ID (Hex)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ATMEL

 

 

 

 

 

 

 

 

 

 

 

0x01F

 

 

 

Reset Register

The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-

 

states Port Pins when reset, the Reset Register can also replace the function of the

 

unimplemented optional JTAG instruction HIGHZ.

 

 

 

A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset TimeOut Period (refer to “Clock Sources” on page 23) after releasing the Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 115.

224 ATmega32(L)

2503F–AVR–12/03

ATmega32(L)

Figure 115. Reset Register

To

TDO

From other Internal and

External Reset Sources

From

Internal Reset

D

Q

TDI

 

 

ClockDR · AVR_RESET

Boundary-scan Chain

The Boundary-scan Chain has the capability of driving and observing the logic levels on

 

the digital I/O pins, as well as the boundary between digital and analog logic for analog

 

circuitry having Off-chip connections.

 

See “Boundary-scan Chain” on page 227 for a complete description.

Boundary-scan Specific

JTAG Instructions

EXTEST; $0

The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not implemented, but all outputs with tri-state capability can be set in highimpedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state.

As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction.

Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having Off-chip connections, the interface between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.

The active states are:

Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

Shift-DR: The Internal Scan Chain is shifted by the TCK input.

Update-DR: Data from the scan chain is applied to output pins.

IDCODE; $1

Optional JTAG instruction selecting the 32-bit ID-register as Data Register. The ID-reg-

 

ister consists of a version number, a device number and the manufacturer code chosen

 

by JEDEC. This is the default instruction after power-up.

The active states are:

Capture-DR: Data in the IDCODE-register is sampled into the Boundary-scan Chain.

Shift-DR: The IDCODE scan chain is shifted by the TCK input.

225

2503F–AVR–12/03

SAMPLE_PRELOAD; $2

 

 

 

 

 

 

 

 

 

 

Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot of

 

the input/output pins without affecting the system operation. However, the output latches

 

are not connected to the pins. The Boundary-scan Chain is selected as Data Register.

 

The active states are:

 

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

 

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

 

• Update-DR: Data from the Boundary-scan Chain is applied to the output latches.

 

However, the output latches are not connected to the pins.

AVR_RESET; $C

The AVR specific public JTAG instruction for forcing the AVR device into the Reset

 

mode or releasing the JTAG Reset source. The TAP controller is not reset by this

 

instruction. The one bit Reset Register is selected as Data Register. Note that the reset

 

will be active as long as there is a logic 'one' in the Reset Chain. The output from this

 

chain is not latched.

The active states are:

Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; $F

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

Capture-DR: Loads a logic “0” into the Bypass Register.

Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Related

Register in I/O Memory

MCU Control and Status

The MCU Control and Status Register contains control bits for general MCU functions,

Register – MCUCSR

and provides information on which reset source caused an MCU Reset.

 

 

 

Bit

7

6

5

4

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

MCUCSR

 

 

JTD

ISC2

JTRF

WDRF

BORF

EXTRF

 

PORF

 

Read/Write

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

 

 

Initial Value

0

0

0

 

See Bit Description

 

 

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

226 ATmega32(L)

2503F–AVR–12/03

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