- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Parity Generator
- •Disabling the Transmitter
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Features
- •Application Section
- •BLS – Boot Loader Section
- •Read-While-Write and no Read-While-Write Flash Sections
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •SPI Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega32 Rev. A
- •Datasheet Change Log for ATmega32
- •Changes from Rev. 2503E-09/03 to Rev. 2503F-12/03
- •Changes from Rev. 2503D-02/03 to Rev. 2503E-09/03
- •Changes from Rev. 2503C-10/02 to Rev. 2503D-02/03
- •Changes from Rev. 2503B-10/02 to Rev. 2503C-10/02
- •Changes from Rev. 2503A-03/02 to Rev. 2503B-10/02
- •Table of Contents
Features
•High-performance, Low-power AVR®8-bit Microcontroller
•Advanced RISC Architecture
–131 Powerful Instructions – Most Single-clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 16 MIPS Throughput at 16 MHz
–On-chip 2-cycle Multiplier
•Nonvolatile Program and Data Memories
–32K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
–Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation
–1024 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
–2K Byte Internal SRAM
–Programming Lock for Software Security
•JTAG (IEEE std. 1149.1 Compliant) Interface
–Boundary-scan Capabilities According to the JTAG Standard
–Extensive On-chip Debug Support
–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•Peripheral Features
–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
–Real Time Counter with Separate Oscillator
–Four PWM Channels
–8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
–Byte-oriented Two-wire Serial Interface
–Programmable Serial USART
–Master/Slave SPI Serial Interface
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
•Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection
–Internal Calibrated RC Oscillator
–External and Internal Interrupt Sources
–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby
•I/O and Packages
–32 Programmable I/O Lines
–40-pin PDIP, 44-lead TQFP, and 44-pad MLF
•Operating Voltages
–2.7 - 5.5V for ATmega32L
–4.5 - 5.5V for ATmega32
•Speed Grades
–0 - 8 MHz for ATmega32L
–0 - 16 MHz for ATmega32
•Power Consumption at 1 MHz, 3V, 25°C for ATmega32L
–Active: 1.1 mA
–Idle Mode: 0.35 mA
–Power-down Mode: < 1 µA
8-bit Microcontroller with 32K Bytes In-System Programmable Flash
ATmega32
ATmega32L
Preliminary
2503F–AVR–12/03
Pin Configurations
Disclaimer
Figure 1. Pinouts ATmega32
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PDIP |
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(XCK/T0) PB0 |
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PB4 |
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RESET |
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AREF |
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VCC |
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GND |
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AVCC |
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XTAL2 |
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PC7 (TOSC2) |
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XTAL1 |
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(RXD) PD0 |
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PC5 (TDI) |
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PC3 (TMS) |
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PC2 (TCK) |
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(OC1B) PD4 |
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PC1 (SDA) |
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(OC1A) PD5 |
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PC0 (SCL) |
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(ICP) PD6 |
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PD7 (OC2) |
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TQFP/MLF
(MOSI) PB5 |
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PB4 (SS) |
PB3 (AIN1/OC0) |
PB2 (AIN0/INT2) |
PB1 (T1) |
PB0 (XCK/T0) |
GND VCC PA0 (ADC0) |
PA1 (ADC1) |
PA2 (ADC2) |
PA3 (ADC3) |
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PA4 (ADC4) |
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(MISO) PB6 |
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PA5 (ADC5) |
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(SCK) PB7 |
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PA6 (ADC6) |
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PA7 (ADC7) |
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VCC |
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AREF |
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GND |
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GND |
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XTAL2 |
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AVCC |
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XTAL1 |
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PC7 (TOSC2) |
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(RXD) PD0 |
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PC6 (TOSC1) |
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(TXD) PD1 |
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PC5 (TDI) |
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(INT0) PD2 |
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PC4 (TDO) |
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PD3 PD4 PD5 PD6 PD7 |
VCC GND PC0 PC1 PC2 PC3 |
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(INT1) |
(OC1B) |
(OC1A) |
(ICP) |
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(SCL) |
(SDA) |
(TCK) |
(TMS) |
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2 ATmega32(L)
2503F–AVR–12/03