ATmega32(L)
Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connection.
Scanning the Digital Port Pins Figure 116 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn
– function, and a bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are not used in the following description.
The Boundary-scan logic is not included in the figures in the datasheet. Figure 117 shows a simple digital Port Pin as described in the section “I/O Ports” on page 47. The Boundary-scan details from Figure 116 replaces the dashed box in Figure 117.
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Register value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 117 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry.
Figure 116. Boundary-scan Cell for Bidirectional Port Pin with Pull-up Function.
ShiftDR |
To Next Cell |
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EXTEST |
Vcc |
Pullup Enable (PUE) |
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0 |
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FF2 |
LD2 |
1 |
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D |
Q |
D Q |
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G |
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Output Control (OC) 
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FF1 |
LD1 |
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D Q |
D Q |
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G |
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Output Data (OD) 
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LD0 |
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Input Data (ID)
From Last Cell |
ClockDR |
UpdateDR |
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2503F–AVR–12/03
Figure 117. General Port Pin Schematic Diagram(1)
Boundary-scan and the Twowire Interface
PUExn |
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PUD |
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Q |
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DDxn |
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Q CLR |
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RESET |
WDx |
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OCxn |
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RDx |
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Pxn |
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BUS |
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DATA |
ODxn |
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PORTxn |
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Q CLR |
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IDxn |
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RESET |
WPx |
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SLEEP |
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RRx |
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SYNCHRONIZER |
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RPx |
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PINxn |
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Q |
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CLK I/O |
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PUD: |
PULLUP DISABLE |
WDx: |
WRITE DDRx |
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PUExn: |
PULLUP ENABLE for pin Pxn |
RDx: |
READ DDRx |
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OCxn: |
OUTPUT CONTROL for pin Pxn |
WPx: |
WRITE PORTx |
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ODxn: |
OUTPUT DATA to pin Pxn |
RRx: |
READ PORTx REGISTER |
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IDxn: |
INPUT DATA from pin Pxn |
RPx: |
READ PORTx PIN |
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SLEEP: |
SLEEP CONTROL |
CLK I/O : |
I/O CLOCK |
Note: |
1. See Boundary-scan descriptin for details. |
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The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the scan-chain; Two-wire Interface Enable – TWIEN. As shown in Figure 118, the TWIEN signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general scan cell as shown in Figure 122 is attached to the TWIEN signal.
Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-scan.
2.Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention.
ATmega32(L)
Figure 118. Additional Scan Signal for the Two-wire Interface
PUExn
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Slew-rate Limited |
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IDxn |
Scanning the RESET Pin |
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active |
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high logic for High Voltage Parallel Programming. An observe-only cell as shown in Fig- |
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ure 119 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; |
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RSTHV. |
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Figure 119. Observe-only Cell |
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ShiftDR |
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To System Logic |
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FF1 |
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0 |
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D |
Q |
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From ClockDR
Previous
Cell
Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low Frequency Crystal Oscillator, and Ceramic Resonator.
Figure 120 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock output is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections.
229
2503F–AVR–12/03
Figure 120. Boundary-scan Cells for Oscillators and Clock Options
XTAL1/TOSC1 XTAL2/TOSC2
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Oscillator |
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EXTEST |
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FF1 |
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From ClockDR |
UpdateDR |
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From ClockDR |
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Previous |
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Table 90 summaries the scan registers for the external clock pin XTAL1, Oscillators with
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Table 90. Scan Signals for the Oscillators(1)(2)(3)
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Scanned Clock Line |
Enable Signal |
Scanned Clock Line |
Clock Option |
when not Used |
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EXTCLKEN |
EXTCLK (XTAL1) |
External Clock |
0 |
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OSCON |
OSCCK |
External Crystal |
0 |
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External Ceramic |
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Resonator |
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RCOSCEN |
RCCK |
External RC |
1 |
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OSC32EN |
OSC32CK |
Low Freq. External Crystal |
0 |
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TOSKON |
TOSCK |
32 kHz Timer Oscillator |
0 |
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Notes: 1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is preferred.
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3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, |
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the clock configuration is considered fixed for a given application. The user is advised |
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to scan the same clock option as to be used in the final system. The enable signals |
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are supported in the scan chain because the system logic can disable clock options |
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in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not |
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provided. The INTCAP fuses are not supported in the scan-chain, so the boundary |
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scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless |
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the fuse is correctly programmed. |
Scanning the Analog |
The relevant Comparator signals regarding Boundary-scan are shown in Figure 121. |
Comparator |
The Boundary-scan cell from Figure 122 is attached to each of these signals. The sig- |
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nals are described in Table 91. |
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The Comparator need not be used for pure connectivity testing, since all analog inputs |
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are shared with a digital port pin as well. |
230 ATmega32(L)
ATmega32(L)
Figure 121. Analog Comparator
BANDGAP
REFERENCE
ACBG
ACO
AC_IDLE
ACME
ADCEN 
ADC MULTIPLEXER
OUTPUT
Figure 122. General Boundary-scan Cell used for Signals for Comparator and ADC
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Next |
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ShiftDR |
Cell |
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EXTEST |
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From Digital Logic/ |
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0 |
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From Analog Ciruitry |
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To Analog Circuitry/ |
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To Digital Logic |
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Q |
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D Q |
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From ClockDR UpdateDR
Previous
Cell
231
2503F–AVR–12/03
