SPI Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 114 on page 268, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.

Data Polling Flash

When a page is being programmed into the Flash, reading an address location within

the page being programmed will give the value $FF. At the time the device is ready for a

new page, the programmed value will read correctly. This is used to determine when the

next page can be written. Note that the entire page is written simultaneously and any

address within the page can be used for polling. Data polling of the Flash will not work

for the value $FF, so when programming this value, the user will have to wait for at least

tWD_FLASH before programming the next page. As a chip erased device contains $FF in

all locations, programming of addresses that are meant to contain $FF, can be skipped.

See Table 115 for tWD_FLASH value

Data Polling EEPROM

When a new byte has been written and is being programmed into EEPROM, reading the

address location being programmed will give the value $FF. At the time the device is

ready for a new byte, the programmed value will read correctly. This is used to deter-

mine when the next byte can be written. This will not work for the value $FF, but the user

should have the following in mind: As a chip erased device contains $FF in all locations,

programming of addresses that are meant to contain $FF, can be skipped. This does

not apply if the EEPROM is re-programmed without chip erasing the device. In this

case, data polling cannot be used for the value $FF, and the user will have to wait at

least tWD_EEPROM before programming the next byte. See Table 115 for tWD_EEPROM

value.

Table 115. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

Symbol

tWD_FLASH

tWD_EEPROM

tWD_ERASE

Figure 137. SPI Serial Programming Waveforms

SERIAL DATA INPUT

MSB

LSB

(MOSI)

SERIAL DATA OUTPUT

MSB

LSB

(MISO)

SPI Serial Programming

For Characteristics of SPI module, see “SPI Timing Characteristics” on page 289.

Characteristics

Programming via the

Programming through the JTAG interface requires control of the four JTAG specific

JTAG Interface

pins: TCK, TMS, TDI and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The

device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR

must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low.

Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available

for programming. This provides a means of using the JTAG pins as normal port pins in

running mode while still allowing In-System Programming via the JTAG interface. Note

that this technique can not be used when using the JTAG pins for Boundary-scan or On-

chip Debug. In these cases the JTAG pins must be dedicated for this purpose.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific JTAG

The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instruc-

Instructions

tions useful for Programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format.

The text describes which Data Register is selected as path between TDI and TDO for

each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can

also be used as an idle state between JTAG sequences. The state machine sequence

for changing the instruction word is shown in Figure 138.