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ATmega32(L)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

An External Reset is generated by a low level on the

 

pin. Reset pulses longer

 

 

 

RESET

 

 

than the minimum pulse width (see Table 15) will generate a reset, even if the clock is

 

 

not running. Shorter pulses are not guaranteed to generate a reset. When the applied

 

 

signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay

 

 

counter starts the MCU after the Time-out period tTOUT has expired.

 

 

Figure 18. External Reset During Operation

 

 

 

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Brown-out Detection

ATmega32 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC

 

level during operation by comparing it to a fixed trigger level. The trigger level for the

 

BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),

 

or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike

 

free Brown-out Detection. The hysteresis on the detection level should be interpreted as

 

VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.

 

The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is

 

enabled (BODEN programmed), and VCC decreases to a value below the trigger level

 

(VBOT- in Figure 19), the Brown-out Reset is immediately activated. When VCC increases

 

above the trigger level (VBOT+ in Figure 19), the delay counter starts the MCU after the

 

Time-out period tTOUT has expired.

 

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level

 

for longer than tBOD given in Table 15.

 

Figure 19. Brown-out Reset During Operation

VCC

VBOT+

 

VBOT-

RESET

 

TIME-OUT

tTOUT

INTERNAL

 

RESET

 

37

2503F–AVR–12/03

Watchdog Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

 

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

 

tTOUT. Refer to page 39 for details on operation of the Watchdog Timer.

 

Figure 20. Watchdog Reset During Operation

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CK

MCU Control and Status

The MCU Control and Status Register provides information on which reset source

Register – MCUCSR

caused an MCU Reset.

 

 

 

 

 

 

 

 

Bit

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTD

ISC2

JTRF

WDRF

BORF

EXTRF

PORF

MCUCSR

 

Read/Write

R/W

R/W

R

R/W

R/W

R/W

R/W

R/W

 

 

Initial Value

0

0

0

 

See Bit Description

 

 

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

38 ATmega32(L)

2503F–AVR–12/03

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