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ATmega32(L)

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

Table 85. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

 

 

 

 

0

0

0

2

 

 

 

 

0

0

1

2

 

 

 

 

0

1

0

4

 

 

 

 

0

1

1

8

 

 

 

 

1

0

0

16

 

 

 

 

1

0

1

32

 

 

 

 

1

1

0

64

 

 

 

 

1

1

1

128

 

 

 

 

The ADC Data Register –

ADCL and ADCH

ADLAR = 0

Bit

15

14

13

12

11

10

9

8

 

 

ADC9

ADC8

ADCH

 

 

 

 

 

 

 

 

 

 

 

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADCL

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

Read/Write

R

R

R

R

R

R

R

R

 

 

R

R

R

R

R

R

R

R

 

Initial Value

0

0

0

0

0

0

0

0

 

 

0

0

0

0

0

0

0

0

 

ADLAR = 1

Bit

15

14

13

12

11

10

9

8

 

 

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

 

 

 

 

 

 

 

 

 

 

 

ADC1

ADC0

ADCL

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

Read/Write

R

R

R

R

R

R

R

R

 

 

R

R

R

R

R

R

R

R

 

Initial Value

0

0

0

0

0

0

0

0

 

 

0

0

0

0

0

0

0

0

 

When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.

215

2503F–AVR–12/03

Special FunctionIO Register –

SFIOR

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 211.

Bit

7

6

5

4

3

2

1

0

 

 

ADTS2

ADTS1

ADTS0

ACME

PUD

PSR2

PSR10

SFIOR

Read/Write

R/W

R/W

R/W

R

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

• Bit 7:5 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 86. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

 

 

 

 

0

0

0

Free Running mode

 

 

 

 

0

0

1

Analog Comparator

 

 

 

 

0

1

0

External Interrupt Request 0

 

 

 

 

0

1

1

Timer/Counter0 Compare Match

 

 

 

 

1

0

0

Timer/Counter0 Overflow

 

 

 

 

1

0

1

Timer/Counter Compare Match B

 

 

 

 

1

1

0

Timer/Counter1 Overflow

 

 

 

 

1

1

1

Timer/Counter1 Capture Event

 

 

 

 

• Bit 4 – Res: Reserved Bit

This bit is reserved for future use in the ATmega32. For ensuring compability with future devices, this bit must be written zero when SFIOR is written.

216 ATmega32(L)

2503F–AVR–12/03

ATmega32(L)

JTAG Interface and

On-chip Debug

System

Features

JTAG (IEEE std. 1149.1 Compliant) Interface

 

Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

 

Debugger Access to:

 

– All Internal Peripheral Units

 

– Internal and External RAM

 

– The Internal Register File

 

– Program Counter

 

– EEPROM and Flash Memories

 

– Extensive On-chip Debug Support for Break Conditions, Including

 

– AVR Break Instruction

 

– Break on Change of Program Memory Flow

 

– Single Step Break

 

– Program Memory Breakpoints on Single Address or Address Range

 

– Data Memory Breakpoints on Single Address or Address Range

 

Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

 

On-chip Debugging Supported by AVR Studio®

Overview

The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

 

• Testing PCBs by using the JTAG Boundary-scan capability

 

• Programming the non-volatile memories, Fuses and Lock bits

 

• On-chip Debugging

 

A brief description is given in the following sections. Detailed descriptions for Program-

 

ming via the JTAG interface, and using the Boundary-scan Chain can be found in the

 

sections “Programming via the JTAG Interface” on page 272 and “IEEE 1149.1 (JTAG)

 

Boundary-scan” on page 223, respectively. The On-chip Debug support is considered

 

being private JTAG instructions, and distributed within ATMEL and to selected third

 

party vendors only.

 

Figure 112 shows a block diagram of the JTAG interface and the On-chip Debug sys-

 

tem. The TAP Controller is a state machine controlled by the TCK and TMS signals. The

 

TAP Controller selects either the JTAG Instruction Register or one of several Data Reg-

 

isters as the scan chain (Shift Register) between the TDI input and TDO output. The

 

Instruction Register holds JTAG instructions controlling the behavior of a Data Register.

 

The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers

 

used for board-level testing. The JTAG Programming Interface (actually consisting of

 

several physical and virtual Data Registers) is used for JTAG Serial Programming via

 

the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for

 

On-chip Debugging only.

Test Access Port – TAP The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are:

TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.

TCK: Test Clock. JTAG operation is synchronous to TCK.

TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains).

TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

217

2503F–AVR–12/03

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debugger to be able to detect external reset sources. The debuggerbta can also pull the RESET pin low to reset the whole system, assuming only open collectors on the reset line are used in the application.

Figure 112. Block Diagram

I/O PORT 0

DEVICE BOUNDARY

 

 

 

 

 

BOUNDARY SCAN CHAIN

 

 

TDI

 

 

JTAG PROGRAMMING

 

 

 

 

TDO

 

TAP

 

 

 

 

 

INTERFACE

 

 

 

 

TCK

 

 

 

 

 

CONTROLLER

 

 

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERNAL

AVR CPU

 

 

 

 

 

FLASH

Address

 

 

 

 

 

 

SCAN

PC

 

 

 

 

INSTRUCTION

MEMORY

Data

 

 

 

 

CHAIN

Instruction

 

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

 

 

 

 

REGISTER

BREAKPOINT

 

 

 

 

 

M

 

UNIT

 

FLOW CONTROL

 

 

 

 

BYPASS

 

 

 

ANALOG PERIPHERIAL UNITS

Analog inputs

 

U

 

 

UNIT

 

 

REGISTER

 

 

DIGITAL

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PERIPHERAL

 

 

 

 

 

 

UNITS

 

 

BREAKPOINT

 

 

 

 

 

 

SCAN CHAIN

 

 

 

 

 

 

 

 

 

 

 

 

JTAG / AVR CORE

 

 

 

 

ADDRESS

 

 

 

COMMUNICATION

 

 

 

 

OCD STATUS

 

INTERFACE

 

lines

 

 

DECODER

 

 

 

 

 

 

 

 

 

 

AND CONTROL

 

 

 

 

 

 

 

 

 

 

 

Control & Clock

 

 

 

 

 

I/O PORT n

 

 

 

218 ATmega32(L)

2503F–AVR–12/03

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