- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Parity Generator
- •Disabling the Transmitter
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Features
- •Overview
- •Test Access Port – TAP
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Features
- •Application Section
- •BLS – Boot Loader Section
- •Read-While-Write and no Read-While-Write Flash Sections
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •SPI Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega32 Rev. A
- •Datasheet Change Log for ATmega32
- •Changes from Rev. 2503E-09/03 to Rev. 2503F-12/03
- •Changes from Rev. 2503D-02/03 to Rev. 2503E-09/03
- •Changes from Rev. 2503C-10/02 to Rev. 2503D-02/03
- •Changes from Rev. 2503B-10/02 to Rev. 2503C-10/02
- •Changes from Rev. 2503A-03/02 to Rev. 2503B-10/02
- •Table of Contents
ATmega32(L)
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the ADC.
Table 85. ADC Prescaler Selections
ADPS2 |
ADPS1 |
ADPS0 |
Division Factor |
|
|
|
|
0 |
0 |
0 |
2 |
|
|
|
|
0 |
0 |
1 |
2 |
|
|
|
|
0 |
1 |
0 |
4 |
|
|
|
|
0 |
1 |
1 |
8 |
|
|
|
|
1 |
0 |
0 |
16 |
|
|
|
|
1 |
0 |
1 |
32 |
|
|
|
|
1 |
1 |
0 |
64 |
|
|
|
|
1 |
1 |
1 |
128 |
|
|
|
|
The ADC Data Register –
ADCL and ADCH
ADLAR = 0
Bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
|
|
– |
– |
– |
– |
– |
– |
ADC9 |
ADC8 |
ADCH |
|
|
|
|
|
|
|
|
|
|
|
ADC7 |
ADC6 |
ADC5 |
ADC4 |
ADC3 |
ADC2 |
ADC1 |
ADC0 |
ADCL |
|
|
|
|
|
|
|
|
|
|
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Read/Write |
R |
R |
R |
R |
R |
R |
R |
R |
|
|
R |
R |
R |
R |
R |
R |
R |
R |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
ADLAR = 1
Bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
|
|
ADC9 |
ADC8 |
ADC7 |
ADC6 |
ADC5 |
ADC4 |
ADC3 |
ADC2 |
ADCH |
|
|
|
|
|
|
|
|
|
|
|
ADC1 |
ADC0 |
– |
– |
– |
– |
– |
– |
ADCL |
|
|
|
|
|
|
|
|
|
|
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Read/Write |
R |
R |
R |
R |
R |
R |
R |
R |
|
|
R |
R |
R |
R |
R |
R |
R |
R |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
215
2503F–AVR–12/03
Special FunctionIO Register –
SFIOR
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 211.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
ADTS2 |
ADTS1 |
ADTS0 |
– |
ACME |
PUD |
PSR2 |
PSR10 |
SFIOR |
Read/Write |
R/W |
R/W |
R/W |
R |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bit 7:5 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 86. ADC Auto Trigger Source Selections
ADTS2 |
ADTS1 |
ADTS0 |
Trigger Source |
|
|
|
|
0 |
0 |
0 |
Free Running mode |
|
|
|
|
0 |
0 |
1 |
Analog Comparator |
|
|
|
|
0 |
1 |
0 |
External Interrupt Request 0 |
|
|
|
|
0 |
1 |
1 |
Timer/Counter0 Compare Match |
|
|
|
|
1 |
0 |
0 |
Timer/Counter0 Overflow |
|
|
|
|
1 |
0 |
1 |
Timer/Counter Compare Match B |
|
|
|
|
1 |
1 |
0 |
Timer/Counter1 Overflow |
|
|
|
|
1 |
1 |
1 |
Timer/Counter1 Capture Event |
|
|
|
|
• Bit 4 – Res: Reserved Bit
This bit is reserved for future use in the ATmega32. For ensuring compability with future devices, this bit must be written zero when SFIOR is written.
216 ATmega32(L)
2503F–AVR–12/03
ATmega32(L)
JTAG Interface and
On-chip Debug
System
Features |
• JTAG (IEEE std. 1149.1 Compliant) Interface |
|
• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard |
|
• Debugger Access to: |
|
– All Internal Peripheral Units |
|
– Internal and External RAM |
|
– The Internal Register File |
|
– Program Counter |
|
– EEPROM and Flash Memories |
|
– Extensive On-chip Debug Support for Break Conditions, Including |
|
– AVR Break Instruction |
|
– Break on Change of Program Memory Flow |
|
– Single Step Break |
|
– Program Memory Breakpoints on Single Address or Address Range |
|
– Data Memory Breakpoints on Single Address or Address Range |
|
• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface |
|
• On-chip Debugging Supported by AVR Studio® |
Overview |
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for |
|
• Testing PCBs by using the JTAG Boundary-scan capability |
|
• Programming the non-volatile memories, Fuses and Lock bits |
|
• On-chip Debugging |
|
A brief description is given in the following sections. Detailed descriptions for Program- |
|
ming via the JTAG interface, and using the Boundary-scan Chain can be found in the |
|
sections “Programming via the JTAG Interface” on page 272 and “IEEE 1149.1 (JTAG) |
|
Boundary-scan” on page 223, respectively. The On-chip Debug support is considered |
|
being private JTAG instructions, and distributed within ATMEL and to selected third |
|
party vendors only. |
|
Figure 112 shows a block diagram of the JTAG interface and the On-chip Debug sys- |
|
tem. The TAP Controller is a state machine controlled by the TCK and TMS signals. The |
|
TAP Controller selects either the JTAG Instruction Register or one of several Data Reg- |
|
isters as the scan chain (Shift Register) between the TDI input and TDO output. The |
|
Instruction Register holds JTAG instructions controlling the behavior of a Data Register. |
|
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers |
|
used for board-level testing. The JTAG Programming Interface (actually consisting of |
|
several physical and virtual Data Registers) is used for JTAG Serial Programming via |
|
the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for |
|
On-chip Debugging only. |
Test Access Port – TAP The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are:
•TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.
•TCK: Test Clock. JTAG operation is synchronous to TCK.
•TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains).
•TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
217
2503F–AVR–12/03
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debugger to be able to detect external reset sources. The debuggerbta can also pull the RESET pin low to reset the whole system, assuming only open collectors on the reset line are used in the application.
Figure 112. Block Diagram
I/O PORT 0
DEVICE BOUNDARY
|
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BOUNDARY SCAN CHAIN |
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TDI |
|
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JTAG PROGRAMMING |
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TDO |
|
TAP |
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||
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INTERFACE |
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TCK |
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CONTROLLER |
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TMS |
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INTERNAL |
AVR CPU |
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FLASH |
Address |
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SCAN |
PC |
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||
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INSTRUCTION |
MEMORY |
Data |
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CHAIN |
Instruction |
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REGISTER |
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ID |
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REGISTER |
BREAKPOINT |
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M |
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UNIT |
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FLOW CONTROL |
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BYPASS |
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ANALOG PERIPHERIAL UNITS |
Analog inputs |
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U |
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UNIT |
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REGISTER |
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DIGITAL |
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X |
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PERIPHERAL |
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UNITS |
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BREAKPOINT |
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SCAN CHAIN |
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JTAG / AVR CORE |
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ADDRESS |
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COMMUNICATION |
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OCD STATUS |
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INTERFACE |
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lines |
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DECODER |
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AND CONTROL |
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Control & Clock |
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I/O PORT n |
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218 ATmega32(L)
2503F–AVR–12/03