- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E(PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •In-System Reprogrammable Flash Program memory
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •Address Latch Requirements
- •Pull-up and Bus Keeper
- •Timing
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •Moving Interrupts between Application and Boot Space
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Single USART
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Analog Comparator
- •Features
- •Application Section
- •Boot Loader Lock bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock bits by SPM
- •Reading the Fuse and Lock bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Program and Data Memory Lock bits
- •Fuse bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8515(L) Rev. B
- •Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
- •Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
- •Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
- •Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
- •Table of Contents
ATmega8515(L)
Errata |
The revision letter in this section refers to the revision of the ATmega8515 device. |
ATmega8515(L) Rev. B There are no errata for this revision of ATmega8515.
247
2512G–AVR–03/05
Datasheet Revision
History
Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision.
1.MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”.
2.Updated “Electrical Characteristics” on page 195
3.Updated “Ordering Information” on page 242.
1. Updated “Calibrated Internal RC Oscillator” on page 38.
1.Removed “Preliminary” from the datasheet.
2.Updated Table 18 on page 45 and “Absolute Maximum Ratings” and “DC Characteristics” in “Electrical Characteristics” on page 195.
3.Updated chapter “ATmega8515 Typical Characteristics” on page 205.
1.Added “EEPROM Write During Power-down Sleep Mode” on page 22.
2.Improved the description in “Phase Correct PWM Mode” on page 87.
3.Corrected OCn waveforms in Figure 53 on page 110.
4.Added note under “Filling the Temporary Buffer (page loading)” on page 171 about writing to the EEPROM during an SPM page load.
5.Updated Table 93 on page 193.
6.Updated “Packaging Information” on page 244.
1.Added “Using all Locations of External Memory Smaller than 64 KB” on page 30.
2.Removed all TBD.
3.Added description about calibration values for 2, 4, and 8 MHz.
4.Added variation in frequency of “External Clock” on page 39.
5.Added note about VBOT, Table 18 on page 45.
6.Updated about “Unconnected pins” on page 63.
7.Updated “16-bit Timer/Counter1” on page 96, Table 51 on page 118 and Table 52 on page 119.
248 ATmega8515(L)
2512G–AVR–03/05
ATmega8515(L)
Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
8.Updated “Enter Programming Mode” on page 182, “Chip Erase” on page 182, Figure 77 on page 185, and Figure 78 on page 186.
9.Updated “Electrical Characteristics” on page 195, “External Clock Drive” on page 197, Table 96 on page 197 and Table 97 on page 198, “SPI Timing Characteristics” on page 198 and Table 98 on page 200.
10.Added “Errata” on page 248.
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
249
2512G–AVR–03/05