- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E(PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •In-System Reprogrammable Flash Program memory
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •Address Latch Requirements
- •Pull-up and Bus Keeper
- •Timing
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •Moving Interrupts between Application and Boot Space
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Single USART
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Analog Comparator
- •Features
- •Application Section
- •Boot Loader Lock bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock bits by SPM
- •Reading the Fuse and Lock bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Program and Data Memory Lock bits
- •Fuse bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8515(L) Rev. B
- •Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
- •Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
- •Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
- •Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
- •Table of Contents
ATmega8515(L)
Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 38.
Table 38. Port E Pins Alternate Functions
Port Pin |
Alternate Function |
|
|
|
|
PE2 |
OC1B (Timer/Counter1 Output Compare B Match Output) |
|
|
|
|
PE1 |
ALE (Address Latch Enable to External Memory) |
|
|
|
|
PE0 |
ICP (Timer/Counter1 Input Capture Pin) |
|
INT2 (External Interrupt 2 Input) |
||
|
||
|
|
The alternate pin configuration is as follows:
• OC1B – Port E, Bit 2
OC1B, Output Compare Match B output: The PE2 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDE2 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.
• ALE – Port E, Bit 1
ALE is the external Data memory Address Latch Enable signal.
• ICP/INT2 – Port E, Bit 0
ICP – Input Capture Pin: The PE0 pin can act as an Input Capture pin for
Timer/Counter1.
INT2, External Interrupt Source 2: The PE0 pin can serve as an external interrupt source.
Table 39 relate the alternate functions of Port E to the overriding signals shown in Figure 33 on page 63.
Table 39. Overriding Signals for Alternate Functions PE2..PE0
Signal Name |
PE2 |
PE1 |
PE0 |
|
|
|
|
PUOE |
0 |
SRE |
0 |
|
|
|
|
PUOV |
0 |
0 |
0 |
|
|
|
|
DDOE |
0 |
SRE |
0 |
|
|
|
|
DDOV |
0 |
1 |
0 |
|
|
|
|
PVOE |
OC1B OVERRIDE ENABLE |
SRE |
0 |
|
|
|
|
PVOV |
OC1B |
ALE |
0 |
|
|
|
|
DIEOE |
0 |
0 |
INT2 ENABLED |
|
|
|
|
DIEOV |
0 |
0 |
1 |
|
|
|
|
DI |
0 |
0 |
INT2 INPUT, ICP INPUT |
|
|
|
|
AIO |
– |
– |
– |
|
|
|
|
73
2512G–AVR–03/05