- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E(PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •In-System Reprogrammable Flash Program memory
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •Address Latch Requirements
- •Pull-up and Bus Keeper
- •Timing
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •Moving Interrupts between Application and Boot Space
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Single USART
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Analog Comparator
- •Features
- •Application Section
- •Boot Loader Lock bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock bits by SPM
- •Reading the Fuse and Lock bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Program and Data Memory Lock bits
- •Fuse bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8515(L) Rev. B
- •Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
- •Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
- •Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
- •Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
- •Table of Contents
Features
•High-performance, Low-power AVR® 8-bit Microcontroller
•RISC Architecture
–130 Powerful Instructions – Most Single Clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 16 MIPS Throughput at 16 MHz
–On-chip 2-cycle Multiplier
•Nonvolatile Program and Data Memories
–8K Bytes of In-System Self-programmable Flash
Endurance: 10,000 Write/Erase Cycles
–Optional Boot Code Section with Independent Lock bits In-System Programming by On-chip Boot Program True Read-While-Write Operation
–512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
–512 Bytes Internal SRAM
–Up to 64K Bytes Optional External Memory Space
–Programming Lock for Software Security
•Peripheral Features
–One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
–Three PWM Channels
–Programmable Serial USART
–Master/Slave SPI Serial Interface
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
•Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection
–Internal Calibrated RC Oscillator
–External and Internal Interrupt Sources
–Three Sleep Modes: Idle, Power-down and Standby
•I/O and Packages
–35 Programmable I/O Lines
–40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
•Operating Voltages
–2.7 - 5.5V for ATmega8515L
–4.5 - 5.5V for ATmega8515
•Speed Grades
–0 - 8 MHz for ATmega8515L
–0 - 16 MHz for ATmega8515
8-bit Microcontroller with 8K Bytes In-System Programmable Flash
ATmega8515
ATmega8515L
Rev. 2512G–AVR–03/05
Pin Configurations
Figure 1. Pinout ATmega8515
(MOSI) PB5 1 (MISO) PB6 2 (SCK) PB7 3 RESET 4 (RXD) PD0 5 NC* 6 (TXD) PD1 7
(INT0) PD2 8 (INT1) PD3 9 (XCK) PD4 10 (OC1A) PD5 11
PDIP
(OC0/T0) PB0 |
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1 |
40 |
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VCC |
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(T1) PB1 |
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2 |
39 |
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PA0 (AD0) |
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(AIN0) PB2 |
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3 |
38 |
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PA1 (AD1) |
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(AIN1) PB3 |
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4 |
37 |
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PA2 (AD2) |
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(SS) PB4 |
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5 |
36 |
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PA3 (AD3) |
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(MOSI) PB5 |
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6 |
35 |
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PA4 (AD4) |
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(MISO) PB6 |
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7 |
34 |
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PA5 (AD5) |
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(SCK) PB7 |
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8 |
33 |
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PA6 (AD6) |
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9 |
32 |
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PA7 (AD7) |
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RESET |
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(RXD) PD0 |
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10 |
31 |
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PE0 (ICP/INT2) |
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(TDX) PD1 |
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11 |
30 |
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PE1 (ALE) |
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(INT0) PD2 |
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12 |
29 |
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PE2 (OC1B) |
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(INT1) PD3 |
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13 |
28 |
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PC7 (A15) |
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(XCK) PD4 |
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14 |
27 |
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PC6 (A14) |
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(OC1A) PD5 |
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PC5 (A13) |
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(WR) PD6 |
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16 |
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PC4 (A12) |
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PC3 (A11) |
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(RD) |
PD7 |
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XTAL2 |
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18 |
23 |
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PC2 (A10) |
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XTAL1 |
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19 |
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PC1 (A9) |
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GND |
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20 |
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PC0 (A8) |
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TQFP/MLF |
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PLCC |
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PB4 (SS) |
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PB3 (AIN1) |
PB2 (AIN0) |
PB1 (T1) |
PB0 (OC0/T0) |
NC* |
VCC |
PA0 (AD0) |
PA1 (AD1) |
PA2 (AD2) |
PA3 (AD3) |
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PB4 (SS) |
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PB3 (AIN1) |
PB2 (AIN0) |
PB1 (T1) |
PB0 (OC0/T0) |
NC* |
VCC |
PA0 (AD0) |
PA1 (AD1) |
PA2 (AD2) |
PA3 (AD3) |
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44 |
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41 |
40 |
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38 |
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35 |
34 |
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6 |
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1 |
44 |
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(MOSI) PB5 |
PA4 (AD4) |
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33 |
PA4 (AD4) |
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39 |
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32 |
PA5 (AD5) |
(MISO) PB6 |
8 |
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38 |
PA5 (AD5) |
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31 |
PA6 (AD6) |
(SCK) PB7 |
9 |
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37 |
PA6 (AD6) |
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30 |
PA7 (AD7) |
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RESET |
10 |
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36 |
PA7 (AD7) |
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29 |
PE0 (ICP/INT2) |
(RXD) PD0 |
11 |
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35 |
PE0 (ICP/INT2) |
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28 |
NC* |
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NC* |
12 |
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NC* |
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27 |
PE1 (ALE) |
(TXD) PD1 |
13 |
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33 |
PE1 (ALE) |
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26 |
PE2 (OC1B) |
(INT0) PD2 |
14 |
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32 |
PE2 (OC1B) |
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25 |
PC7 (A15) |
(INT1) PD3 |
15 |
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31 |
PC7 (A15) |
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24 |
PC6 (A14) |
(XCK) PD4 |
16 |
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30 |
PC6 (A14) |
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23 |
PC5 (A13) |
(OC1A) PD5 |
17 |
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29 |
PC5 (A13) |
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18 |
19 |
20 |
21 |
22 |
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24 |
25 |
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27 |
28 |
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(WR) PD6 12 |
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(RD) PD7 13 |
XTAL2 14 |
XTAL1 15 |
GND 16 |
NC* 17 |
(A8) PC0 18 |
(A9) PC1 19 |
(A10) PC2 20 |
(A11) PC3 21 |
(A12) PC4 22 |
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(WR) PD6 |
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(RD) PD7 |
XTAL2 |
XTAL1 |
GND |
NC* |
(A8) PC0 |
(A9) PC1 |
(A10) PC2 |
(A11) PC3 |
(A12) PC4 |
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NOTES:
1.MLF bottom pad should be soldered to ground.
2.* NC = Do not connect (May be used in future devices)
2 ATmega8515(L)
2512G–AVR–03/05