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External Data Memory Timing

Table 98. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state

				8 MHz Oscillator			Variable Oscillator

	Symbol		Parameter	Min	Max		Min		Max	Unit

0	1/tCLCL		Oscillator Frequency				0.0		16	MHz
1	tLHLL		ALE Pulse Width	115		1.0tCLCL-10				ns
2	t	AVLL	Address Valid A to ALE Low	57.5		0.5t	-5(1)			ns
		AVLL					CLCL
			Address Hold After ALE Low,	5			5
3a	tLLAX_ST		write access	5			5			ns
3a	tLLAX_ST		write access							ns
			Address Hold after ALE Low,	5			5
3b	tLLAX_LD		read access	5			5			ns
3b	tLLAX_LD		read access							ns
4	t	AVLLC	Address Valid C to ALE Low	57.5		0.5t	-5(1)			ns
		AVLLC					CLCL
5	tAVRL		Address Valid to RD Low	115		1.0tCLCL-10				ns
6	tAVWL		Address Valid to WR Low	115		1.0tCLCL-10				ns
7	t	LLWL	ALE Low to WR Low	47.5	67.5	0.5t	-15(2)	0.5t	+5(2)	ns
		LLWL				CLCL			CLCL
8	t	LLRL	ALE Low to RD Low	47.5	67.5	0.5t	-15(2)	0.5t	+5(2)	ns
		LLRL				CLCL			CLCL
9	tDVRH		Data Setup to RD High	40			40			ns
10	tRLDV		Read Low to Data Valid		75			1.0tCLCL-50		ns
11	tRHDX		Data Hold After RD High	0			0			ns
12	tRLRH		RD Pulse Width	115		1.0tCLCL-10				ns
13	t	DVWL	Data Setup to WR Low	42.5		0.5t	-20(1)			ns
		DVWL				CLCL
14	tWHDX		Data Hold After WR High	115		1.0tCLCL-10				ns
15	tDVWH		Data Valid to WR High	125		1.0tCLCL				ns
16	tWLWH		WR Pulse Width	115		1.0tCLCL-10				ns

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 99. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

			8 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		200		2.0tCLCL-50	ns
12	tRLRH	RD Pulse Width	240		2.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	240		2.0tCLCL		ns
16	tWLWH	WR Pulse Width	240		2.0tCLCL-10		ns

200 ATmega8515(L)

2512G–AVR–03/05

ATmega8515(L)

Table 100. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		325		3.0tCLCL-50	ns
12	tRLRH	RD Pulse Width	365		3.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	375		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	365		3.0tCLCL-10		ns

Table 101. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		325		3.0tCLCL-50	ns
12	tRLRH	RD Pulse Width	365		3.0tCLCL-10		ns
14	tWHDX	Data Hold After WR High	240		2.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	375		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	365		3.0tCLCL-10		ns

Table 102. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state

			4 MHz Oscillator			Variable Oscillator

	Symbol	Parameter	Min	Max		Min		Max	Unit

0	1/tCLCL	Oscillator Frequency				0.0		8	MHz
1	tLHLL	ALE Pulse Width	235		tCLCL-15				ns
2	t	Address Valid A to ALE Low	115		0.5t	-10(1)			ns
	AVLL					CLCL
		Address Hold After ALE Low,	5			5
3a	tLLAX_ST	write access	5			5			ns
3a	tLLAX_ST	write access							ns
		Address Hold after ALE Low,	5			5
3b	tLLAX_LD	read access	5			5			ns
3b	tLLAX_LD	read access							ns
4	t	Address Valid C to ALE Low	115		0.5t	-10(1)			ns
	AVLLC					CLCL
5	tAVRL	Address Valid to RD Low	235		1.0tCLCL-15				ns
6	tAVWL	Address Valid to WR Low	235		1.0tCLCL-15				ns
7	t	ALE Low to WR Low	115	130	0.5t	-10(2)	0.5t	+5(2)	ns
	LLWL					CLCL		CLCL
8	t	ALE Low to RD Low	115	130	0.5t	-10(2)	0.5t	+5(2)	ns
	LLRL					CLCL		CLCL
9	tDVRH	Data Setup to RD High	45			45			ns
10	tRLDV	Read Low to Data Valid		190			1.0tCLCL-60		ns
11	tRHDX	Data Hold After RD High	0			0			ns

201

2512G–AVR–03/05



Table 102. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state					(Continued)

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

12	tRLRH	RD Pulse Width	235		1.0tCLCL-15		ns
13	t	Data Setup to WR Low	105		0.5t -20(1)		ns
	DVWL				CLCL
14	tWHDX	Data Hold After WR High	235		1.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	250		1.0tCLCL		ns
16	tWLWH	WR Pulse Width	235		1.0tCLCL-15		ns

Table 103. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		440		2.0tCLCL-60	ns
12	tRLRH	RD Pulse Width	485		2.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	500		2.0tCLCL		ns
16	tWLWH	WR Pulse Width	485		2.0tCLCL-15		ns

Table 104. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		690		3.0tCLCL-60	ns
12	tRLRH	RD Pulse Width	735		3.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	750		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	735		3.0tCLCL-15		ns

Table 105. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		690		3.0tCLCL-60	ns
12	tRLRH	RD Pulse Width	735		3.0tCLCL-15		ns
14	tWHDX	Data Hold After WR High	485		2.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	750		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	735		3.0tCLCL-15		ns

202 ATmega8515(L)

2512G–AVR–03/05

ATmega8515(L)

Figure 89. External Memory Timing (SRWn1 = 0, SRWn0 = 0

	T1	T2		T3	T4
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. Addr.			Address
				15
		2	3a	13
DA7:0	Prev. Data	Address	XX	Data
		6		16	14
		6		16
WR
			3b	9	11
DA7:0 (XMBK = 0)		Address		Data
		5		10
			8	12

Figure 90. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

	T1	T2		T3	T4	T5
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. Addr.			Address
					15
		2	3a	13
DA7:0	Prev. Data	Address	XX		Data
		6			16	14
		6			16
WR
			3b		9	11
DA7:0 (XMBK = 0)		Address			Data
		5		10
			8		12

Write

Read

Write

Read

203

2512G–AVR–03/05

Figure 91. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

		T1			T2		T3	T4	T5	T6
System Clock (CLKCPU)
				1
ALE
				4		7
A15:8		Prev. Addr.						Address
								15
				2	3a	13
DA7:0		Prev. Data		Address		XX		Data
					6			16		14
								16

WR
					3b			9		11
DA7:0 (XMBK = 0)				Address				Data
					5		10
						8		12
RD
Figure 92.	External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)
		T1		T2		T3	T4	T5	T6	T7
System Clock (CLKCPU)
			1
ALE
			4		7
A15:8	Prev. Addr.						Address
							15
			2	3a	13
DA7:0	Prev. Data		Address		XX		Data
				6			16			14
				6			16
WR
				3b			9		11
DA7:0 (XMBK = 0)			Address				Data
				5		10
					8		12

Write

Read

Read Write

Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).

204 ATmega8515(L)

2512G–AVR–03/05

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