- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Port D (PD7..PD0)
- •Port E(PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •In-System Reprogrammable Flash Program memory
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •Address Latch Requirements
- •Pull-up and Bus Keeper
- •Timing
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •Moving Interrupts between Application and Boot Space
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •Modes of Operation
- •Phase Correct PWM Mode
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Single USART
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Analog Comparator
- •Features
- •Application Section
- •Boot Loader Lock bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock bits by SPM
- •Reading the Fuse and Lock bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Program and Data Memory Lock bits
- •Fuse bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8515(L) Rev. B
- •Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
- •Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
- •Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
- •Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
- •Table of Contents
ATmega8515(L)
Table 84. Fuse Low Byte
Fuse Low Byte |
Bit no |
Description |
Default value |
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BODLEVEL |
7 |
Brown-out Detector trigger |
1 |
(unprogrammed) |
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level |
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BODEN |
6 |
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1 |
(unprogrammed, BOD |
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Brown-out Detector enable |
disabled) |
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SUT1 |
5 |
Select start-up time |
1 |
(unprogrammed)(1) |
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SUT0 |
4 |
Select start-up time |
0 |
(programmed)(1) |
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CKSEL3 |
3 |
Select Clock source |
0 |
(programmed)(2) |
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CKSEL2 |
2 |
Select Clock source |
0 |
(programmed)(2) |
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CKSEL1 |
1 |
Select Clock source |
0 |
(programmed)(2) |
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CKSEL0 |
0 |
Select Clock source |
1 |
(unprogrammed)(2) |
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Notes: 1. The default value of SUT1..0 results in maximum start-up time. See Table 13 on page 38 for details.
2.The default setting of CKSEL3..0 results in internal RC Oscillator @ 1 MHz. See Table 5 on page 34 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Latching of Fuses |
The fuse values are latched when the device enters Programming mode and changes of |
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the fuse values will have no effect until the part leaves Programming mode. This does |
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not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses |
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Signature Bytes
Calibration Byte
Calibration Byte
All Atmel microcontrollers have a 3-byte signature code which identifies the device. This code can be read in both Serial and Parallel mode, also when the device is locked. The three bytes reside in a separate address space.
For the ATmega8515 the signature bytes are:
1.$000: $1E (indicates manufactured by Atmel).
2.$001: $93 (indicates 8KB Flash memory).
3.$002: $06 (indicates ATmega8515 device when $001 is $93).
The ATmega8515 has a one-byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address $000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.
The ATmega8515 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row high byte of the addresses 0x000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded manually, see “Oscillator Calibration Register – OSCCAL” on page 38 for details.
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2512G–AVR–03/05
Parallel Programming
Parameters, Pin
Mapping, and
Commands
Signal Names
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8515. Pulses are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the ATmega8515 are referenced by signal names describing their functionality during parallel programming, see Figure 75 and Table 85. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 87.
When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 88.
Figure 75. Parallel Programming
+5V
RDY/BSY
PD1
VCC
OE
PD2
PB7 - PB0 
DATA
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
+12 V
RESET
BS2 PA0
XTAL1
GND
Table 85. Pin Name Mapping
Signal Name in Programming Mode |
Pin Name |
I/O |
Function |
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RDY/BSY |
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PD1 |
O |
1: Device is ready for new |
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PD2 |
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Output Enable (Active low) |
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PD3 |
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Write Pulse (Active low) |
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BS1 |
PD4 |
I |
Byte Select 1 (“0” selects low |
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XA0 |
PD5 |
I |
XTAL Action Bit 0 |
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XA1 |
PD6 |
I |
XTAL Action Bit 1 |
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PAGEL |
PD7 |
I |
Program memory and EEPROM |
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data Page Load |
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BS2 |
PA0 |
I |
Byte Select 2 (“0” selects low |
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DATA |
PB7-0 |
I/O |
Bi-directional Data bus (Output |
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180 ATmega8515(L)
2512G–AVR–03/05
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ATmega8515(L) |
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Table 86. Pin Values used to Enter Programming Mode |
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PAGEL |
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Prog_enable[3] |
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XA1 |
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Prog_enable[2] |
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XA0 |
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Prog_enable[1] |
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BS1 |
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Prog_enable[0] |
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Table 87. XA1 and XA0 Coding |
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XA1 |
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XA0 |
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Action when XTAL1 is Pulsed |
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Load Flash or EEPROM Address (High or low address byte determined by |
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Load Data (High or Low data byte for Flash determined by BS1) |
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Load Command |
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No Action, Idle |
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Table 88. Command Byte Bit Coding |
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Command Byte |
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Command Executed |
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1000 0000 |
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Chip Erase |
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0100 0000 |
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Write Fuse bits |
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0010 0000 |
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Write Lock bits |
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0001 0000 |
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Write Flash |
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0001 0001 |
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Write EEPROM |
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0000 1000 |
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Read Signature Bytes and Calibration byte |
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0000 0100 |
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Read Fuse and Lock bits |
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0000 0010 |
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Read Flash |
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0000 0011 |
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Read EEPROM |
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Table 89. No. of Words in a Page and No. of Pages in the Flash
Flash Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
PCMSB |
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4K words (8K bytes) |
32 words |
PC[4:0] |
128 |
PC[11:5] |
11 |
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Table 90. No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
EEAMSB |
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512 bytes |
4 bytes |
EEA[1:0] |
128 |
EEA[8:2] |
8 |
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181
2512G–AVR–03/05
