- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E(PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •In-System Reprogrammable Flash Program memory
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •Address Latch Requirements
- •Pull-up and Bus Keeper
- •Timing
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •Moving Interrupts between Application and Boot Space
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Single USART
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Analog Comparator
- •Features
- •Application Section
- •Boot Loader Lock bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock bits by SPM
- •Reading the Fuse and Lock bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Program and Data Memory Lock bits
- •Fuse bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8515(L) Rev. B
- •Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
- •Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
- •Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
- •Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
- •Table of Contents
ATmega8515(L)
Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 32.
Table 32. Port C Pins Alternate Functions
Port Pin |
Alternate Function |
|
|
PC7 |
A15 (External memory interface address bit 15) |
|
|
PC6 |
A14 (External memory interface address bit 14) |
|
|
PC5 |
A13 (External memory interface address bit 13) |
|
|
PC4 |
A12 (External memory interface address bit 12) |
|
|
PC3 |
A11 (External memory interface address bit 11) |
|
|
PC2 |
A10 (External memory interface address bit 10) |
|
|
PC1 |
A9 (External memory interface address bit 9) |
|
|
PC0 |
A8 (External memory interface address bit 8) |
|
|
• A15 – Port C, Bit 7
A15, External memory interface address bit 15.
• A14 – Port C, Bit 6
A14, External memory interface address bit 14.
• A13 – Port C, Bit 5
A13, External memory interface address bit 13.
• A12 – Port C, Bit 4
A12, External memory interface address bit 12.
• A11 – Port C, Bit 3
A11, External memory interface address bit 11.
• A10 – Port C, Bit 2
A10, External memory interface address bit 10.
• A9 – Port C, Bit 1
A9, External memory interface address bit 9.
• A8 – Port C, Bit 0
A8, External memory interface address bit 8.
Table 33 and Table 34 relate the alternate functions of Port C to the overriding signals shown in Figure 33 on page 63.
69
2512G–AVR–03/05
Table 33. Overriding Signals for Alternate Functions in PC7..PC4
Signal Name |
PC7/A15 |
PC6/A14 |
PC5/A13 |
PC4/A12 |
|
|
|
|
|
PUOE |
SRE • (XMM<1) |
SRE • (XMM<2) |
SRE • (XMM<3) |
SRE • (XMM<4) |
|
|
|
|
|
PUOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DDOE |
SRE • (XMM<1) |
SRE • (XMM<2) |
SRE • (XMM<3) |
SRE • (XMM<4) |
|
|
|
|
|
DDOV |
1 |
1 |
1 |
1 |
|
|
|
|
|
PVOE |
SRE • (XMM<1) |
SRE • (XMM<2) |
SRE • (XMM<3) |
SRE • (XMM<4) |
|
|
|
|
|
PVOV |
A15 |
A14 |
A13 |
A12 |
|
|
|
|
|
DIEOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
DIEOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DI |
– |
– |
– |
– |
|
|
|
|
|
AIO |
– |
– |
– |
– |
|
|
|
|
|
Table 34. Overriding Signals for Alternate Functions in PC3..PC0
Signal Name |
PC3/A11 |
PC2/A10 |
PC1/A9 |
PC0/A8 |
|
|
|
|
|
PUOE |
SRE • (XMM<5) |
SRE • (XMM<6) |
SRE • (XMM<7) |
SRE • (XMM<7) |
|
|
|
|
|
PUOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DDOE |
SRE • (XMM<5) |
SRE • (XMM<6) |
SRE • (XMM<7) |
SRE • (XMM<7) |
|
|
|
|
|
DDOV |
1 |
1 |
1 |
1 |
|
|
|
|
|
PVOE |
SRE • (XMM<5) |
SRE • (XMM<6) |
SRE • (XMM<7) |
SRE • (XMM<7) |
|
|
|
|
|
PVOV |
A11 |
A10 |
A9 |
A8 |
|
|
|
|
|
DIEOE |
0 |
0 |
0 |
0 |
|
|
|
|
|
DIEOV |
0 |
0 |
0 |
0 |
|
|
|
|
|
DI |
– |
– |
– |
– |
|
|
|
|
|
AIO |
– |
– |
– |
– |
|
|
|
|
|
70 ATmega8515(L)
2512G–AVR–03/05
ATmega8515(L)
Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 35.
Table 35. Port D Pins Alternate Functions
Port Pin |
|
Alternate Function |
||
|
|
|
|
|
PD7 |
|
|
|
(Read Strobe to External Memory) |
|
RD |
|||
|
|
|
|
|
PD6 |
|
|
|
(Write Strobe to External Memory) |
|
WR |
|||
|
|
|||
PD5 |
OC1A (Timer/Counter1 Output Compare A Match Output) |
|||
|
|
|
||
PD4 |
|
XCK (USART External Clock Input/Output) |
||
|
|
|
||
PD3 |
|
INT1 (External Interrupt 1 Input) |
||
|
|
|
||
PD2 |
|
INT0 (External Interrupt 0 Input) |
||
|
|
|
||
PD1 |
|
TXD (USART Output Pin) |
||
|
|
|
||
PD0 |
|
RXD (USART Input Pin) |
||
|
|
|
|
|
The alternate pin configuration is as follows:
• RD – Port D, Bit 7
RD is the External Data memory read control strobe.
• WR – Port D, Bit 6
WR is the External Data memory write control strobe.
• OC1A – Port D, Bit 5
OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
• XCK – Port D, Bit 4
XCK, USART External Clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK pin is active only when USART operates in Synchronous mode.
• INT1 – Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.
• INT0/XCK1 – Port D, Bit 2
INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt source.
XCK1, External Clock. The Data Direction Register (DDD2) controls whether the clock is output (DDD2 set) or input (DDD2 cleared).
• TXD – Port D, Bit 1
TXD, Transmit Data (Data output pin for USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1.
• RXD – Port D, Bit 0
RXD, Receive Data (Data input pin for USART). When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit.
71
2512G–AVR–03/05
Table 36 and Table 37 relate the alternate functions of Port D to the overriding signals shown in Figure 33 on page 63.
Table 36. Overriding Signals for Alternate Functions PD7..PD4
|
|
|
|
|
|
|
|
|
|
|
|
|
Signal Name |
PD7/RD |
|
PD6/WR |
PD5/OC1A |
PD4/XCK |
|||||||
|
|
|
|
|
|
|
|
|
||||
PUOE |
SRE |
SRE |
0 |
0 |
||||||||
|
|
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|
|
|
|
|
|
|
||
PUOV |
0 |
|
|
|
0 |
|
|
|
0 |
0 |
||
|
|
|
|
|
|
|
|
|
||||
DDOE |
SRE |
SRE |
0 |
0 |
||||||||
|
|
|
|
|
|
|
|
|
|
|
||
DDOV |
1 |
|
|
|
1 |
|
|
|
0 |
0 |
||
|
|
|
|
|
|
|
|
|
|
|
||
PVOE |
|
SRE |
|
SRE |
OC1A ENABLE |
XCK OUTPUT ENABLE |
||||||
|
|
|
|
|
|
|
|
|
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|
|
|
PVOV |
|
|
|
|
|
|
|
|
|
|
OC1A |
XCK OUTPUT |
RD |
WR |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
||
DIEOE |
0 |
|
|
|
0 |
|
|
|
0 |
0 |
||
|
|
|
|
|
|
|
|
|
|
|
||
DIEOV |
0 |
|
|
|
0 |
|
|
|
0 |
0 |
||
|
|
|
|
|
|
|
|
|
|
|
||
DI |
|
– |
|
– |
– |
XCK INPUT |
||||||
|
|
|
|
|
|
|
|
|
|
|
||
AIO |
|
– |
|
– |
– |
– |
||||||
|
|
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|
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|
|
|
|
|
|
|
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Table 37. Overriding Signals for Alternate Functions in PD3..PD0
Signal Name |
PD3/INT1 |
PD2/INT0 |
PD1/TXD |
PD0/RXD |
||
|
|
|
|
|
||
PUOE |
0 |
0 |
TXEN0 |
RXEN0 |
||
|
|
|
|
|
|
|
PUOV |
0 |
0 |
0 |
PORTD0 • |
|
|
PUD |
||||||
|
|
|
|
|
||
DDOE |
0 |
0 |
TXEN0 |
RXEN0 |
||
|
|
|
|
|
|
|
DDOV |
0 |
0 |
1 |
0 |
|
|
|
|
|
|
|
|
|
PVOE |
0 |
0 |
TXEN0 |
0 |
|
|
|
|
|
|
|
|
|
PVOV |
0 |
0 |
TXD |
0 |
|
|
|
|
|
|
|
|
|
DIEOE |
INT1 ENABLE |
INT0 ENABLE |
0 |
0 |
|
|
|
|
|
|
|
|
|
DIEOV |
1 |
1 |
0 |
0 |
|
|
|
|
|
|
|
||
DI |
INT1 INPUT |
INT0 INPUT |
– |
RXD |
||
|
|
|
|
|
||
AIO |
– |
– |
– |
– |
||
|
|
|
|
|
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72 ATmega8515(L)
2512G–AVR–03/05