- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E(PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •In-System Reprogrammable Flash Program memory
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •Address Latch Requirements
- •Pull-up and Bus Keeper
- •Timing
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •Moving Interrupts between Application and Boot Space
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Single USART
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Analog Comparator
- •Features
- •Application Section
- •Boot Loader Lock bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock bits by SPM
- •Reading the Fuse and Lock bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Program and Data Memory Lock bits
- •Fuse bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8515(L) Rev. B
- •Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
- •Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
- •Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
- •Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
- •Table of Contents
Memory
Programming
Program and Data Memory Lock bits
2512G–AVR–03/05
ATmega8515(L)
The ATmega8515 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 82. The Lock bits can only be erased to “1” with the Chip Erase command.
Table 81. Lock Bit Byte(1)
Lock Bit Byte |
Bit no |
Description |
Default Value |
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7 |
– |
1 (unprogrammed) |
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6 |
– |
1 (unprogrammed) |
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BLB12 |
5 |
Boot Lock bit |
1 (unprogrammed) |
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BLB11 |
4 |
Boot Lock bit |
1 (unprogrammed) |
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BLB02 |
3 |
Boot Lock bit |
1 (unprogrammed) |
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BLB01 |
2 |
Boot Lock bit |
1 (unprogrammed) |
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LB2 |
1 |
Lock bit |
1 (unprogrammed) |
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LB1 |
0 |
Lock bit |
1 (unprogrammed) |
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Note: 1. “1” means unprogrammed, “0” means programmed
Table 82. Lock Bit Protection Modes(2)
Memory Lock bits |
Protection Type |
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LB Mode |
LB2 |
LB1 |
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1 |
1 |
1 |
No memory lock features enabled. |
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Further programming of the Flash and EEPROM is |
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2 |
1 |
0 |
disabled in Parallel and Serial Programming mode. The |
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Fuse bits are locked in both Serial and Parallel |
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Programming mode.(1) |
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Further programming and verification of the Flash and |
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3 |
0 |
0 |
EEPROM is disabled in Parallel and Serial Programming |
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mode. The Fuse bits are locked in both Serial and Parallel |
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Programming mode.(1) |
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BLB0 Mode |
BLB02 |
BLB01 |
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1 |
1 |
1 |
No restrictions for SPM or LPM accessing the Application |
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section. |
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2 |
1 |
0 |
SPM is not allowed to write to the Application section. |
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SPM is not allowed to write to the Application section, and |
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LPM executing from the Boot Loader section is not |
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3 |
0 |
0 |
allowed to read from the Application section. If Interrupt |
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Vectors are placed in the Boot Loader section, interrupts |
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are disabled while executing from the Application section. |
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LPM executing from the Boot Loader section is not |
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4 |
0 |
1 |
allowed to read from the Application section. If Interrupt |
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Vectors are placed in the Boot Loader section, interrupts |
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are disabled while executing from the Application section. |
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BLB1 Mode |
BLB12 |
BLB11 |
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177