- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E(PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •In-System Reprogrammable Flash Program memory
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •Address Latch Requirements
- •Pull-up and Bus Keeper
- •Timing
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •Moving Interrupts between Application and Boot Space
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Single USART
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Analog Comparator
- •Features
- •Application Section
- •Boot Loader Lock bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock bits by SPM
- •Reading the Fuse and Lock bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Program and Data Memory Lock bits
- •Fuse bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega8515(L) Rev. B
- •Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05
- •Changes from Rev. 2512F-12/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512D-02/03 to Rev. 2512E-09/03
- •Changes from Rev. 2512C-10/02 to Rev. 2512D-02/03
- •Changes from Rev. 2512B-09/02 to Rev. 2512C-10/02
- •Changes from Rev. 2512A-04/02 to Rev. 2512B-09/02
- •Table of Contents
Table 82. Lock Bit Protection Modes(2) (Continued)
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Memory Lock bits |
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Protection Type |
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1 |
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1 |
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1 |
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No restrictions for SPM or LPM accessing the Boot Loader |
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section. |
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2 |
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1 |
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0 |
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SPM is not allowed to write to the Boot Loader section. |
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SPM is not allowed to write to the Boot Loader section, |
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and LPM executing from the Application section is not |
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3 |
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0 |
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0 |
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allowed to read from the Boot Loader section. If Interrupt |
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Vectors are placed in the Application section, interrupts |
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are disabled while executing from the Boot Loader |
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section. |
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LPM executing from the Application section is not allowed |
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4 |
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0 |
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1 |
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to read from the Boot Loader section. If Interrupt Vectors |
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are placed in the Application section, interrupts are |
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disabled while executing from the Boot Loader section. |
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Notes: 1. Program the Fuse bits before programming the Lock bits. |
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2. “1” means unprogrammed, “0” means programmed |
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Fuse bits |
The ATmega8515 has two Fuse bytes. Table 83 and Table 84 describe briefly the func- |
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tionality of all the fuses and how they are mapped into the fuse bytes. Note that the |
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Fuses are read as logical zero, “0”, if they are programmed. |
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Table 83. Fuse High Byte |
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Fuse High Byte |
Bit no |
Description |
Default Value |
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S8515C |
7 |
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AT90S4414/8515 compatibility |
1 (unprogrammed) |
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mode |
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WDTON |
6 |
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Watchdog Timer always on |
1 (unprogrammed) |
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SPIEN(1)(2) |
5 |
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Enable Serial Program and Data |
0 (programmed, SPI prog. |
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Downloading |
enabled) |
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CKOPT(3) |
4 |
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Oscillator options |
1 (unprogrammed) |
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EESAVE |
3 |
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EEPROM memory is preserved |
1 (unprogrammed, |
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through the Chip Erase |
EEPROM not preserved) |
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BOOTSZ1 |
2 |
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Select Boot Size (see Table 78 for |
0 (programmed)(4) |
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details) |
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BOOTSZ0 |
1 |
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Select Boot Size (see Table 78 for |
0 (programmed)(4) |
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details) |
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BOOTRST |
0 |
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Select Reset Vector |
1 (unprogrammed) |
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Notes: 1. See “AT90S4414/8515 Compatibility Mode” on page 4 for details.
2.The SPIEN Fuse is not accessible in serial programming mode.
3.The CKOPT Fuse functionality depends on the setting of the CKSEL bits. See “Clock Sources” on page 34. for details.
4.The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 78 on page 175.
178 ATmega8515(L)
2512G–AVR–03/05