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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320tci6618.pdf

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INFORMATION ADVANCE

TMS320TCI6618

Communications Infrastructure KeyStone SoC

SPRS688—February 2011	www.ti.com

2.5.1 Boot Device Field

The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 ‘‘Boot Mode Pins: Boot Device Values’’ shows the supported boot modes.

Table 2-3	Boot Mode Pins: Boot Device Values

Bit	Field	Value	Description
2-0	Boot Device	0	No boot

		1	Serial Rapid I/O

		2	Ethernet (SGMII) (PA driven from core clk)

		3	Ethernet (SGMII) (PA driver from PA clk)

4PCI

5I2C

6SPI

7HyperLink

2.5.2Device Configuration Field

The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode

2.5.2.1 No Boot Device Configuration

Figure 2-3		No Boot Configuration Bit Fields

	9		8	7	6		5	4		3
		Reserved		Wait Enable		Sub-Mode			Reserved

Table 2-4		No Boot Configuration Bit Field Descriptions

Bit	Field		Value	Description
9-8	Reserved			Reserved

7	Wait Enable		0	Wait enable disabled
			1	Wait enable enabled

6-5	Sub-Mode		0	No Boot
			1-3	Reserved

4-3	Reserved			Reserved

2.5.2.2 Serial Rapid I/O Boot Device Configuration

The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.

Figure 2-4	Serial Rapid I/O Device Configuration Bit Fields

9		8		7	6		5	4		3
Lane Setup			Data Rate			Ref Clock			Reserved

28	Copyright 2011 Texas Instruments Incorporated

			TMS320TCI6618
			Communications Infrastructure KeyStone SoC
www.ti.com			SPRS688—February 2011
www.ti.com
Table 2-5	Serial Rapid I/O Configuration Bit Field Descriptions

Bit	Field	Value	Description
9	Lane Setup	0	Port Configured as 4 ports each 1 lane wide (4 -1× ports)
		1	Port Configured as 2 ports 2 lanes wide (2 – 2× ports)

8-7	Data Rate	0	Data Rate = 1.25 GBs
		1	Data Rate = 2.5 GBs
		2	Data Rate = 3.125 GBs
		3	Data Rate = 5.0 GBs

6-5	Ref Clock	0	Reference Clock = 156.25 MHz
		1	Reference Clock = 250 MHz
		2	Reference Clock = 312.5 MHz

4-3	Reserved	0-3	Reserved

In SRIO boot mode, both the message mode and DirectIO mode will be enabled by default. If use of the memory reserved for received messages is required and reception of messages cannot be prevented, the master can disable the message mode by writing to the boot table and generating a boot restart.

2.5.2.3 Ethernet (SGMII) Boot Device Configuration

Figure 2-5			Ethernet (SGMII) Device Configuration Bit Fields

		9		8		7	6	5	4	3
			SerDes Clock Mult			Ext connection			Dev ID

Table 2-6			Ethernet (SGMII) Configuration Bit Field Descriptions

	Bit	Field			Value			Description
	9-8	SerDes clock mult				The output frequency of the PLL must be 1.25 GBs.
					0	×8 for input clock of 156.25 MHz
					1	×5 for input clock of 250 MHz
					2	×4 for input clock of 312.5 MHz
					3	Reserved

	7-6	Ext connection			0	Mac to Mac connection, master with auto negotiation
					1	Mac to Mac connection, slave, and Mac to Phy
					2	Mac to Mac, forced link
					3	Mac to fiber connection

	5-3	Device ID			0-7	This value is used in the device ID field of the Ethernet-ready frame.

2.5.2.4 PCI Boot Device Configuration

Extra device configuration is provided in the PCI bits in the DEVSTAT register.

Figure 2-6 PCI Device Configuration Bit Fields

9	8	7	6	5	4		3
Reserved		BAR Config				Reserved

ADVANCE INFORMATION

	TMS320TCI6618
	Communications Infrastructure KeyStone SoC
	SPRS688—February 2011												www.ti.com
													www.ti.com
	Table 2-7		PCI Device Configuration Bit Field Descriptions

	Bit	Field			Value					Description
	9	Reserved					Reserved

	8-5	Bar Config			0-0xf		See Table 2-8.

	4-3	Reserved			0-3		Reserved

	Table 2-8		BAR Config / PCIe Window Sizes

							32-Bit Address Translation					64-Bit Address Translation
ADVANCE	BAR cfg		BAR0	BAR1		BAR2		BAR3	BAR4		BAR5	BAR1/2	BAR3/4
ADVANCE	0b0000		PCIe MMRs	32		32		32	32		Clone of BAR4
	0b0000		PCIe MMRs	32		32		32	32		Clone of BAR4

	0b0001			16		16		32	64

	0b0010			16		32		32	64

	0b0011			32		32		32	64

	0b0100			16		16		64	64

INFORMATION	0b0101			16		32		64	64

	0b0110			32		32		64	64
	0b0110			32		32		64	64

	0b0111			32		32		64	128

	0b1000			64		64		128	256

	0b1001			4		128		128	128

	0b1010			4		128		128	256

	0b1011			4		128		256	256
	0b1100											256	256

	0b1101											512	512

	0b1110											1024	1024

	0b1111											2048	2048

2.5.2.5 I2C Boot Device Configuration

2.5.2.5.1 I2C Master Mode

In master mode, the I2C device configuration uses ten bits of device configuration instead of seven as used in other boot modes. In this mode, the device will make the initial read of the I2C EEPROM while the PLL is in bypass mode. The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.

Figure 2-7	I2C Master Mode Device Configuration Bit Fields
12	11	10	9	8	7	6	5	4		3
Reserved	Speed	Address	Mode			Parameter Index
			(0)
			(0)						Reserved
									Reserved

30	Copyright 2011 Texas Instruments Incorporated

				TMS320TCI6618
				Communications Infrastructure KeyStone SoC
www.ti.com				SPRS688—February 2011
www.ti.com
Table 2-9		I2C Master Mode Device Configuration Field Descriptions

Bit	Field		Value	Description
12	Reserved			Reserved

11	Speed		0	I2C data rate set to approximately 20 kHz

		1	I2C fast mode. Data rate set to approximately 400 kHz (will not exceed)
10	Address	0	Boot from I2C EEPROM at I2C bus address 0x50
		1	Boot from I2C EEPROM at I2C bus address 0x51
9	Mode	0	Master mode
		1	Passive mode (see ‘‘I2C Passive Mode’’ on page 31)

8-3	Parameter Index	0-63	Identifies the index of the configuration table initially read from the I2C EEPROM
4-3	Reserved	0-3	Reserved

2.5.2.5.2 I2C Passive Mode

In passive mode, the device does not drive the clock, but simply acks data received on the specified address.

Figure 2-8			I2C Passive Mode Device Configuration Bit Fields
	9			8		7	6	5	4		3
	Mode (1)					Receive I2C Address				Reserved
Table 2-10			I2C Passive Mode Device Configuration Field Descriptions

Bit		Field			Value	Description
9		Mode			0	Master Mode (see ‘‘I2C Master Mode’’ on page 30)
					1	Passive Mode

8-5		Receive I2C Address			0-15	The I2C Bus address the device will listen to for data
4-3		Reserved			0-3	Reserved

2.5.2.6 SPI Boot Device Configuration

In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other boot modes.

Figure 2-9		SPI Device Configuration Bit Fields

12		11	10	9	8		7	6	5	4		3
	Mode		4, 5 Pin	Addr Width		Chip Select		Parameter Table Index			Reserved

Table 2-11		SPI Device Configuration Field Descriptions

Bit	Field		Value					Description
12-11	Mode			Clk Pol / Phase

0Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.

1Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK.

2Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.

3Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK.

4, 5 Pin

4-pin mode used

15-pin mode used

ADVANCE INFORMATION

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