INFORMATION ADVANCE
TMS320TCI6618
Communications Infrastructure KeyStone SoC
SPRS688—February 2011 |
www.ti.com |
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3.3.17 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register is shown in Figure 3-16 and described in Table 3-18.
Figure 3-16 Timer Output Selection Register (TOUTPSEL)
31 |
9 |
8 |
5 |
4 |
3 |
0 |
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Reserved |
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TOUTPSEL1 |
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Reserved |
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TOUTPSEL0 |
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R,+0000000000000000000000000 |
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RW,+0001 |
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0 |
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RW,+0000 |
Legend: R = Read only; RW = Read/Write; -n = value after reset |
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Table 3-18 |
Timer Output Selection Field Description (TOUTPSEL) |
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Bit |
Field |
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Description |
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31-9 |
Reserved |
Reserved |
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8-5 |
TOUTPSEL1 |
Output select for TIMO1 |
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0000: TOUTL0 |
1000: TOUTL4 |
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0001: TOUTH0 |
1001: TOUTH4 |
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0010: TOUTL1 |
1010: TOUTL5 |
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0011: TOUTH1 |
1011: TOUTH5 |
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0100: TOUTL2 |
1100: TOUTL6 |
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0101: TOUTH2 |
1101: TOUTH6 |
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0110: TOUTL3 |
1110: TOUTL7 |
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0111: TOUTH3 |
1111: TOUTH7 |
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4 |
Reserved |
Reserved |
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3-0 |
TOUTPSEL0 |
Output select for TIMO0 |
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0000: TOUTL0 |
1000: TOUTL4 |
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0001: TOUTH0 |
1001: TOUTH4 |
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0010: TOUTL1 |
1010: TOUTL5 |
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0011: TOUTH1 |
1011: TOUTH5 |
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0100: TOUTL2 |
1100: TOUTL6 |
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0101: TOUTH2 |
1101: TOUTH6 |
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0110: TOUTL3 |
1110: TOUTL7 |
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0111: TOUTH3 |
1111: TOUTH7 |
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End of Table 3-18 |
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3.3.18 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through RSTMUX3 for each of the four CorePacs on the TCI6618. These registers are located in Bootcfg memory space. The Timer Output Selection Register is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17 Reset Mux Register (RSTMUX0 through RSTMUX3)
31 |
10 |
9 |
8 |
7 |
5 |
4 |
3 |
1 |
0 |
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Reserved |
EVTSTATCLR |
Reserved |
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DELAY |
EVTSTAT |
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OMODE |
LOCK |
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R, +0000 0000 0000 0000 0000 00 |
RC, +0 |
R, +0 |
RW, +100 |
R, +0 |
RW, +000 |
RW, +0 |
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Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
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Copyright 2011 Texas Instruments Incorporated |
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TMS320TCI6618 |
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Communications Infrastructure KeyStone SoC |
www.ti.com |
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SPRS688—February 2011 |
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Table 3-19 |
Reset Mux Register Field Descriptions |
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Bit |
Field |
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Description |
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31-10 |
Reserved |
Reserved |
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9 |
EVTSTATCLR |
0 = Writing O had no effect |
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1 = Writing 1 to this bit clears the EVTSTAT bit |
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8 |
Reserved |
Reserved |
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7-5 |
DELAY |
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000b = 256 CPU/6 cycles delay between NMI & Local reset, when OMODE = 100b |
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001b |
= 512 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b |
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010b |
= 1024 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b |
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011b |
= 2048 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b |
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100b |
= 4096 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b (Default) |
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101b |
= 8192 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b |
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110b |
= 16384 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b |
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111b |
= 32768 CPU/6 cycles delay between NMI & Local reset, when OMODE=100b |
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4 |
EVTSTAT |
0 = No event received (Default) |
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1 = WD timer event received by Reset Mux block |
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3-1 |
OMODE |
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000b = WD Timer Event input to the Reset Mux block does not cause any output event (Default) |
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001b |
= Reserved |
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010b |
= WD Timer Event input to the Reset Mux block causes local reset input to CorePac |
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011b |
= WD Timer Event input to the Reset Mux block causes NMI input to CorePac |
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100b |
= WD Timer Event input to the Reset Mux block causes NMI input followed by Local reset input to CorePac. Delay |
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between NMI and local reset is set in DELAY bit field. |
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101b |
= WD Timer Event input to the Reset Mux block causes Device Reset to TCI6618 |
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110b |
= Reserved |
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111b |
= Reserved |
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0 |
LOCK |
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0 = Register fields are not locked (Default) |
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1 = Register fields are locked until the next timer reset |
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End of Table 3-19 |
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ADVANCE INFORMATION
Copyright 2011 Texas Instruments Incorporated |
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