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TMS320TCI6618 |
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Communications Infrastructure KeyStone SoC |
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www.ti.com |
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SPRS688—February 2011 |
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6 Device Operating Conditions |
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6.1 Absolute Maximum Ratings |
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Table 6-1 |
Absolute Maximum Ratings (1) |
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Over Operating Case Temperature Range (Unless Otherwise Noted) |
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CVDD |
-0.3 V to TBD V |
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CVDD1 |
-0.3 V to TBD V |
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DVDD15 |
-0.3 V to TBD V |
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DVDD18 |
-0.3 V to TBD V |
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Supply voltage range (2): |
VREFSSTL |
0.49 × DVDD15 to 0.51 × DVDD15 |
INFORMATION |
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VDDT1, VDDT2, VDDT3 |
-0.3 V to TBD V |
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VDDT4, VDDT5, VDDT6 |
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VDDR1, VDDR2, VDDR3 |
-0.3 V to TBD V |
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AVDDA1, AVDDA2, AVDDA3 |
-0.3 V to TBD V |
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VSS Ground |
0 V |
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LVCMOS (1.8V) |
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-0.3 V to TBD V |
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DDR3 |
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-0.3 V to TBD V |
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Input voltage (VI) range: |
I2C |
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-0.3 V to TBD V |
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LVDS |
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-0.3 V to TBD V |
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ADVANCE |
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LJCB |
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-0.3 V to TBD V |
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SERDES |
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-0.3 V to TBD V |
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LVCMOS (1.8V) |
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-0.3 V to TBD V |
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Output voltage (VO) range: |
DDR3 |
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-0.3 V to TBD V |
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I2C |
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-0.3 V to TBD V |
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SERDES |
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-0.3 V to TBD V |
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Commercial |
1-GHz CPU |
0°C to 100°C |
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Operating case temperature range, TC: |
1.2-GHz CPU |
0°C to 95°C |
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Extended |
1-GHz CPU |
-40°C to 100°C |
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1.2-GHz CPU |
-40°C to 95°C |
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LVCMOS (1.8V) |
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Overshoot/undershoot (3) |
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20% Overshoot/Undershoot for 20% of |
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DDR3 |
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Signal Duty Cycle |
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I2C |
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Storage temperature range, Tstg: |
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-65°C to 150°C |
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End of Table 6-1 |
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1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2 All voltage values are with respect to VSS.
3 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be VSS - 0.20 × DVDD18
Copyright 2011 Texas Instruments Incorporated |
89 |
INFORMATION ADVANCE
TMS320TCI6618 |
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Communications Infrastructure KeyStone SoC |
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SPRS688—February 2011 |
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www.ti.com |
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6.2 Recommended Operating Conditions |
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Table 6-2 |
Recommended Operating Conditions (1) (2) |
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Min |
Nom |
Max |
Unit |
CVDD |
SR Core Supply |
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1-GHz CPU |
0.855 |
1 |
1.05 |
V |
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1.2-GHz CPU |
0.855 |
1 |
1.05 |
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CVDD1 |
Core Supply |
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0.95 |
1 |
1.05 |
V |
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DVDD18 |
1.8-V supply I/O voltage |
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1.71 |
1.8 |
1.89 |
V |
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DVDD15 |
1.5-V supply I/O voltage |
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1.425 |
1.5 |
1.575 |
V |
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VREFSSTL |
DDR3 reference voltage |
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0.49 × DVDD15 |
0.5 × DVDD15 |
0.51 × DVDD15 |
V |
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(3) |
SerDes regulator supply |
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1.425 |
1.5 |
1.575 |
V |
VDDRx |
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VDDAx |
PLL analog supply |
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1.71 |
1.8 |
1.89 |
V |
VDDTx |
SerDes termination supply |
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0.95 |
1 |
1.05 |
V |
VSS |
Ground |
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0 |
0 |
0 |
V |
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LVCMOS (1.8 V) |
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0.65 × DVDD18 |
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V |
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VIH |
High-level input voltage |
I2C |
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0.7 × DVDD18 |
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V |
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DDR3 EMIF |
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VREFSSTL + 0.1 |
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V |
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LVCMOS (1.8 V) |
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0.35 × DVDD18 |
V |
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VIL |
Low-level input voltage |
DDR3 EMIF |
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-0.3 |
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VREFSSTL - 0.1 |
V |
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I2C |
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0.3 × DVDD18 |
V |
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Commercial |
1-GHz CPU |
0 |
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100 |
°C |
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TC |
Operating case temperature |
1.2-GHz CPU |
0 |
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95 |
°C |
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Extended |
1-GHz CPU |
-40 |
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100 |
°C |
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1.2-GHz CPU |
-40 |
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95 |
°C |
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End of Table 6-2 |
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1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
2 All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002. 3 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.
90 |
Copyright 2011 Texas Instruments Incorporated |
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TMS320TCI6618 |
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Communications Infrastructure KeyStone SoC |
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||||
www.ti.com |
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SPRS688—February 2011 |
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|||
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6.3 |
Electrical Characteristics |
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Table 6-3 |
Electrical Characteristics |
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Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) |
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Parameter |
Test Conditions (1) |
Min |
Typ |
Max |
Unit |
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LVCMOS (1.8 V) |
IO = IOH |
DVDD18 - 0.45 |
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VOH |
High-level output voltage |
DDR3 |
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DVDD15 - 0.4 |
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V |
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I2C (2) |
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LVCMOS (1.8 V) |
IO = IOL |
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0.45 |
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VOL |
Low-level output voltage |
DDR3 |
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0.4 |
V |
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I2C |
IO = 3 mA, pulled up to 1.8 V |
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0.4 |
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INFORMATION |
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TBD |
No IPD/IPU |
-5 |
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TBD |
μA |
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5 |
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LVCMOS (1.8 V) |
Internal pullup |
50 |
100 |
170 |
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II (3) |
Input current [DC] |
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Internal pulldown |
-170 |
-100 |
-50 |
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I |
2 |
C |
0.1 × DVDD18 V < VI < 0.9 × |
-10 |
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10 |
μA |
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DVDD18 V |
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TBD |
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TBD |
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IOH High-level output current [DC] |
TBD |
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TBD |
mA |
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TBD |
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TBD |
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ADVANCE |
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TBD |
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TBD |
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TBD |
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TBD |
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IOL |
Low-level output current [DC] |
TBD |
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TBD |
mA |
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TBD |
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TBD |
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TBD |
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TBD |
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IOZ (4) |
Off-state output current [DC] |
LVCMOS (1.8 V) |
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-2 |
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2 |
μA |
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End of Table 6-3 |
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1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table. 2 I2C uses open collector IOs and does not have a VOH Minimum.
3 II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and off-state (Hi-Z) output leakage current.
4 IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
Copyright 2011 Texas Instruments Incorporated |
91 |