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TMS320TCI6618

Communications Infrastructure KeyStone SoC

7 TMS320TCI6618 Peripheral Information and Electrical Specifications

This chapter covers the various peripherals on the TMS320TCI6618 device. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.

7.1 Parameter Information

This section describes the conditions used to capture the electrical data seen in this chapter.

The data manual provides timing at the device pin. For output analysis, the transmission line and associated parasitics (vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending on the trace length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end product design. For recommended transmission line lengths, see the appropriate application notes, user guides, and design guides. A transmission line delay of 2 ns was used for all output measurements, except the DDR3, which was evaluated using a 528-ps delay.

Figure 7-1 represents all device outputs, except differential or I2C.

Figure 7-1 Test Load Circuit for AC Timing Measurements

Device

DDR3 Output Test Load

Transmission Line

Zo = 50

4 pF

Data Manual Timing

Reference Point

(Device Terminal)

Device

Output Test Load Excluding DDR3

Transmission Line

Zo = 50

5 pF

All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks.

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels

Vref = VIH MIN (or VOH MIN)

7.1.2 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report in ‘‘Related Documentation from Texas Instruments’’ on page 59. If needed, external logic hardware such as buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (Table 7-1 and Figure 7-4).

Table 7-1 Board-Level Timing Example

(see Figure 7-4)

End of Table 7-1

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