INFORMATION ADVANCE

TMS320TCI6618

Communications Infrastructure KeyStone SoC

The inputs, multiply factor within the PLL, and post-division for each of the chip-level clocks from the PLL output. The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 59 for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see Section 7.8.4 ‘‘Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing’’.

CAUTION—The PLL controller module as described in the see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59 includes a superset of features, some of which are not supported on the TMS320TCI6618 device. The following sections describe the registers that are supported; it should be assumed that any registers not included in these sections is not supported by the device. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.

7.8.1 Main PLL Controller Device-Specific Information

7.8.1.1 Internal Clocks and Maximum Operating Frequencies

The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the DDR3 and the PASS modules) requires a PLL controller to manage the various clock divisions, gating, and synchronization. The Main PLL’s PLL controller has several SYSCLK outputs that are listed below, along with the clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below.

•REFCLK: Full-rate clock for CorePac 0~CorePac 3, RAC, and RSA.

•SYSCLK2: 1/x-rate clock for CorePac (emulation) and the ADTF module. Default rate for this will be 1/3. This is programmable from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.

•SYSCLK3: 1/2-rate clock used to clock the L2/MSMC, TCP3d, HyperLink, CPU/2 SCR, DDR EMIF and CPU/2 EDMA.

•SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs will use this as well.

•SYSCLK5: 1/y-rate clock for system trace module only. Default rate for this will be 1/5. It is configurable and the max configurable clock is 210 MHz and min configuration clock is 32 MHz. The SYSCLK5 can be turned off by software.

•SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT compensated buffers for DDR3 EMIF.

•SYSCLK7: 1/6-rate clock for slow peripherals and sources the SYSCLKOUT output pin.

•SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclck in the system. Default for this will be 1/64. This is programmable from /24 to /80.

•SYSCLK9: 1/12-rate clock for SmartReflex.

•SYSCLK10: 1/3-rate clock for SRIO only.

•SYSCLK11: 1/6-rate clock for PSC only.

Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on TMS320TCI6618 device.