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TMS320TCI6618
Communications Infrastructure KeyStone SoC
www.ti.com |
SPRS688—February 2011 |
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7.3.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 7-6 and defined in Table 7-4.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.
Figure 7-6 |
IO Before Core Power Sequencing |
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Power Stabilization Phase |
Device Initialization Phase |
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POR |
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INFORMATION |
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t5 |
t7 |
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RESETFULL |
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t8 |
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GPIO Config |
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Bits |
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t2a |
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t9 |
t10 |
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RESET |
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t3c |
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ADVANCE |
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t1 |
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t2b |
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CVDD |
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t6 |
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t3a |
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CVDD1 |
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DVDD18 |
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t4 |
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DVDD15 |
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t3b |
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REFCLKP&N |
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DDRCLKP&N |
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RESETSTAT |
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Copyright 2011 Texas Instruments Incorporated |
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