INFORMATION ADVANCE
TMS320TCI6618
Communications Infrastructure KeyStone SoC
SPRS688—February 2011 |
www.ti.com |
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3 Device Configuration
On the TMS320TCI6618 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device are disabled and need to be enabled by software before being used.
3.1 Device Configuration at Device Reset
Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP.
Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state),
the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 76.
Table 3-1 |
TMS320TCI6618 Device Configuration Pins |
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Configuration Pin |
Pin No. |
IPD/IPU (1) |
Functional Description |
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LENDIAN(1) |
(2) |
AJ20 |
IPU |
Device endian mode (LENDIAN). |
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0 |
= Device operates in big endian mode |
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1 |
= Device operates in little endian mode |
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BOOTMODE[12:0] (1) (2) |
AF21, AE20, AD20, |
IPD |
Method of boot. |
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AG19, AE21, AJ19, |
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See ‘‘Boot Modes Supported and PLL Settings’’ on page 27 for more details. See the |
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AH19, AG20, AE18, |
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Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas |
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AF18, AE19, AD19, |
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Instruments’’ on page 59 for detailed information on boot configuration |
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AG18 |
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PCIESSMODE[1:0] (1) (2) |
AD21, AH20 |
IPD |
PCIe Subsystem mode selection. |
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00 = PCIe in end point mode |
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01 = PCIe legacy end point (no support for MSI) |
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10 = PCIe in root complex mode |
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11 = Reserved |
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PCIESSEN (1) (2) |
AJ23 |
IPD |
PCIe subsystem enable/disable. |
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0 |
= PCIE Subsystem is disabled |
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1 |
= PCIE Subsystem is enabled |
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CORECLKSEL(1) |
AB25 |
IPD |
Core clock select. |
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0 |
= SYSCLK is used as the input to Main PLL |
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1 |
= ALTCORECLK is used as the input to Main PLL |
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PACLKSEL(1) |
AD23 |
IPD |
Packet accelerator subsystem clock select. |
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0 |
= SYSCLK / ALTCORECLK (controlled by CORECLKSEL pin) is used as the input to PA_SS |
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PLL |
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1 |
= PASSCLK is used as the input to PASS PLL |
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End of Table 3-1 |
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1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩresistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 76.
2 These signal names are the secondary functions of these pins.
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Copyright 2011 Texas Instruments Incorporated |