INFORMATION ADVANCE

TMS320TCI6618

Communications Infrastructure KeyStone SoC

7.9 DDR3 PLL

The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset, DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.

DDR3 PLL power is supplied externally via the Main PLL power-supply pin (AVDDA2). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 59 for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

Figure 7-31 DDR3 PLL Block Diagram

7.9.1 DDR3 PLL Control Register

The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can be controlled using the DDR3PLLCTL register located in the Bootcfg module. This MMR exists inside the Bootcfg space. To write to this register, software should go through an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.5.3 ‘‘PLL Settings’’ on page 33. See 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 65 for the address location of the registers and locking and unlocking sequences for accessing the registers. This register is reset on POR only.

Legend: RW = Read/Write; -n = value after reset

1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.