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TMS320TCI6618

Communications Infrastructure KeyStone SoC

For more detailed information on the C66x CorePac in the TCI6618 device, see the C66x CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

5.1 Memory Architecture

Each core of the TMS320TCI6618 device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 2048KB multicore shared memory (MSM). All memory on the TCI6618 has a unique location in the memory map (see Table 2-2 ‘‘TMS320TCI6618 Memory Map Summary’’ on page 18.

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

5.1.1 L1P Memory

The L1P memory configuration for the TCI6618 device is as follows:

•Region 0 size is 0K bytes (disabled)

•Region 1 size is 32K bytes with no wait states

Figure 5-2 shows the available SRAM/cache configurations for L1P.

Figure 5-2 TMS320TCI6618 L1P Memory Configurations

TMS320TCI6618

Communications Infrastructure KeyStone SoC

5.1.2 L1D Memory

The L1D memory configuration for the TCI6618 device is as follows:

•Region 0 size is 0K bytes (disabled)

•Region 1 size is 32K bytes with no wait states

Figure 5-3 shows the available SRAM/cache configurations for L1D.

Figure 5-3 TMS320TCI6618 L1D Memory Configurations

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TMS320TCI6618

Communications Infrastructure KeyStone SoC

Global addresses that are accessible to all masters in the system are in all memory local to the processors. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to 0. The aliasing is handled within the CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for CorePac 0's L2 memory.

CorePac 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the four CorePacs as their own L2 base addresses. For CorePac 0, as mentioned, this is equivalent to 0x10800000, for CorePac 1 this is equivalent to 0x11800000, and for CorePac 2 this is equivalent to 0x12800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular CorePac should always use the global address only.

5.1.4 MSM SRAM

The MSM SRAM configuration for the TCI6618 device is as follows:

•Memory size is 2048KB

•The MSM can be configured as shared L2 or shared L3 memory

•Allows extension of external addresses from 2GB to up to 8GB

•Has built in memory protection features

The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on external memory address extension and memory protection features, see the Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

5.1.5 L3 Memory

The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

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