TMS320TCI6618

Communications Infrastructure KeyStone SoC

7.14 HyperLink Peripheral

The TMS320TCI6618 includes the HyperLink for companion chip/die interfaces. This is a four-lane SerDes interface designed to operate at 12.5 Gbps per lane from pin-to-pin and at 18 Gbps per lane from die-to-die.

The interface is used to connect with external accelerators that are manufactured using TI libraries. The Hyperbridge links must be connected with DC coupling.

The interface includes the Serial Station Management Interfaces used to send power management and flow messages between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.

Table 7-70 HyperLink Peripheral Timing Requirements

(see Figure 7-42, Figure 7-43 and Figure 7-44)

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Figure 7-42 HyperLink Station Management Clock Timing

1

2 3

Figure 7-43 HyperLink Station Management Transmit Timing

?_CLK

?_DAT

Figure 7-44 HyperLink Station Management Receive Timing

?_CLK

?_DAT

TMS320TCI6618

Communications Infrastructure KeyStone SoC

7.15 UART Peripheral

The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and UART terminal interface or other UART based peripheral. UART is based on the industry standard TL16C550 asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

CTS

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INFORMATION ADVANCE

CTS

7.16 PCIe Peripheral

The 2 lane PCI express (PCIe) module on TMS320TCI6618 provides an interface between the DSP and other PCIe compliant devices. The PCI Express module provides low pin count, high reliability, and high-speed data transfer at rates of 5.0 Gbps per lane on the serial links. For more information, see the Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

7.17 Packet Accelerator

The packet accelerator provides L2 to L4 classification functionalities. It supports classification for Ethernet, VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as TCP and UDP ports. It maintains 8K multiple-in, multiple-out hardware queues. It also provides checksum capability as well as some QoS capabilities. It enables a single IP address to be used for a multi-core device. It can process up to 1.5 M pps. For more information, see the Packet Accelerator (PA) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.