TMS320TCI6618
Communications Infrastructure KeyStone SoC
www.ti.com |
SPRS688—February 2011 |
|
7.3 Power Supplies
The following sections describe the proper power-supply sequencing and timing needed to properly power on the TCI6618. The various power supply rails and their primary function is listed in Table 7-2 below.
Table 7-2 |
Power Supply Rails on TMS320TCI6618 |
|
|||
|
|
|
|
|
|
Name |
Primary Function |
Voltage |
Notes |
|
|
CVDD |
SmartReflex core supply voltage |
0.9 - 1.1 V |
Variable Core Supply |
|
|
|
|
|
|
|
|
CVDD1 |
Core supply voltage for memory |
1.0 V |
Fixed supply at 1.0 V |
|
|
|
array |
|
|
|
|
|
|
|
|
|
|
VDDT1 |
HyperLink SerDes termination |
1.0 V |
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if |
|
|
|
supply |
|
HyperLink is not in use. |
INFORMATION |
|
|
|
|
|
||
VDDT3 |
AIF SerDes termination supply |
1.0 V |
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if AIF is |
||
|
|||||
|
|
|
not in use. |
|
|
|
|
|
|
|
|
VDDT2 |
SGMII/SRIO/PCIE SerDes |
1.0 V |
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if |
|
|
|
termination supply |
|
SGMII/SRIO/PCIE is not in use. |
|
|
|
|
|
|
|
|
DVDD15 |
1.5-V DDR3 IO supply |
1.5 V |
Fixed supply at 1.5 V |
|
|
|
|
|
|
|
|
VDDR1 |
HyperLink SerDes regulator supply |
1.5 V |
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if |
|
|
|
|
|
HyperLink is not in use. |
|
|
|
|
|
|
|
|
VDDR2 |
PCIE SerDes regulator supply |
1.5 V |
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIE |
|
|
|
|
|
is not in use. |
|
|
|
|
|
|
|
|
VDDR3 |
SGMII SerDes regulator supply |
1.5 V |
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if |
|
|
|
|
|
SGMII is not in use. |
ADVANCE |
|
|
|
|
|
||
AVDDA2 |
DDR3 PLL supply |
1.8 V |
Filtered version of DVDD18. Special considerations for noise. |
||
VDDR4 |
SRIO SerDes regulator supply |
1.5 V |
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SRIO |
|
|
|
|
|
is not in use. |
|
|
VDDR5 |
AIF SerDes regulator supply |
1.5 V |
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if AIF |
|
|
VDDR6 |
|
|
|
|
|
DVDD18 |
1.8-V IO supply |
1.8 V |
Fixed supply at 1.8 V |
|
|
|
|
|
|
|
|
AVDDA1 |
Main PLL supply |
1.8 V |
Filtered version of DVDD18. Special considerations for noise. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AVDDA3 |
PASS PLL supply |
1.8 V |
Filtered version of DVDD18. Special considerations for noise. |
|
|
|
|
|
|
|
|
VREFSSTL |
0.75-V DDR3 reference voltage |
0.75 V |
Should track the 1.5-V supply. Use 1.5 V as source. |
|
|
|
|
|
|
|
|
VSS |
Ground |
GND |
Ground |
|
|
|
|
|
|
|
|
End of Table 7-2 |
|
|
|
||
|
|
|
|
|
|
7.3.1 Power-Up Sequencing
This section defines the requirements for a power up sequencing from a Power-on reset condition. There are two acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO voltages as shown below.
1.CVDD
2.CVDD1, VDDT1-3
3.DVDD18, AVDD1, AVDD2 (HHV)
4.DVDD15, VDDR1-6
The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.
1.DVDD18, AVDD1, AVDD2 (HHV)
2.CVDD
3.CVDD1, VDDT1-3
4.DVDD15, VDDR1-6
Copyright 2011 Texas Instruments Incorporated |
95 |
INFORMATION ADVANCE
TMS320TCI6618
Communications Infrastructure KeyStone SoC
SPRS688—February 2011 |
www.ti.com |
|
The clock input buffers for SYSCLK, ALTCORECLK, DDRCLK, PASSCLK, SRIOSGMIICLK, PCIECLK, and MCMCLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once CVDD is valid, it is acceptable that the P and N legs of these clocks may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation, the clock inputs should be removed from the high impedance state shortly after CVDD is present.
If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled to ground through a 1-kΩresistor. The P leg should be tied to CVDD to ensure it will not have any voltage present until CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could cause damage to the device.
The device initialization is broken into two phases. The first phase consists of the time period from the activation of the first power supply until the point at which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL will trigger the end of the initialization phase but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. The following section has a mention of REFCLK in many places. REFCLK here refers to the clock input that has been selected as the source for the Main PLL. See Figure 7-17 for more details.
96 |
Copyright 2011 Texas Instruments Incorporated |
TMS320TCI6618
Communications Infrastructure KeyStone SoC
www.ti.com |
SPRS688—February 2011 |
|
7.3.1.1 Core-Before-IO Power Sequencing
Figure 7-5 shows the power sequencing and reset control of TMS320TCI6618 for device initialization. POR may be removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified. On the rising edge of POR, the HHV signal will go inactive. REFCLK must always be active before POR can be removed. Core-before-IO power sequencing is defined in Table 7-3.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.
Figure 7-5 |
Core Before IO Power Sequencing |
|
|
|
|
|
Power Stabilization Phase |
Device Initialization Phase |
|
POR |
|
|
|
|
|
|
|
t7 |
|
RESETFULL |
|
|
|
|
|
|
|
|
t8 |
GPIO Config |
|
|
|
|
Bits |
|
|
|
|
|
|
t4b |
t9 |
t10 |
RESET |
|
|
|
|
|
t1 |
t2c |
|
|
CVDD |
|
|
|
|
|
|
|
t6 |
|
|
t2a |
|
|
|
CVDD1 |
|
|
|
|
|
|
t3 |
|
|
DVDD18 |
|
|
|
|
|
|
t4a |
|
|
DVDD15 |
|
|
|
|
|
|
|
t5 |
|
REFCLKP&N |
|
|
|
|
|
|
t2b |
|
|
DDRCLKP&N |
|
|
|
|
RESETSTAT |
|
|
|
|
ADVANCE INFORMATION
Copyright 2011 Texas Instruments Incorporated |
97 |
|
TMS320TCI6618 |
|
|
||||||||||||||||||||||
|
Communications Infrastructure KeyStone SoC |
|
|
||||||||||||||||||||||
|
SPRS688—February 2011 |
|
www.ti.com |
||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
Table 7-3 |
|
Core Before IO Power Sequencing |
|
|
||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Time |
System State |
|
|
|||||||||||||||||||||
|
t1 |
Begin Power Stabilization Phase |
|
|
|||||||||||||||||||||
|
|
• CVDD (core AVS) ramps up. |
|
|
|||||||||||||||||||||
|
|
• |
|
must be held low through the power stabilization phase. Because |
|
|
|
is low, all the core logic that has async reset (created from |
|||||||||||||||||
|
|
POR |
POR |
||||||||||||||||||||||
|
|
|
POR) is put into the reset state. |
|
|
||||||||||||||||||||
|
|
|
|||||||||||||||||||||||
|
t2a |
• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is |
|||||||||||||||||||||||
|
|
|
permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage. |
|
|
||||||||||||||||||||
|
|
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will |
|||||||||||||||||||||||
|
|
|
ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core |
||||||||||||||||||||||
|
|
|
constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1. |
||||||||||||||||||||||
|
|
|
|||||||||||||||||||||||
ADVANCE |
t2b |
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be |
|||||||||||||||||||||||
|
|
before DVDD18 is valid could cause damage to the device. |
|
|
|||||||||||||||||||||
|
|
|
driven with a valid clock or be held in a static state with one leg high and one leg low. |
|
|
||||||||||||||||||||
|
t2c |
• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before |
POR |
goes high |
|||||||||||||||||||||
|
|
|
specified by t6. |
|
|
||||||||||||||||||||
|
t3 |
• DVDD18 (1.8 V) supply is ramped up followed coincidentally by HHV (1.8 V). |
|
|
|||||||||||||||||||||
|
|
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18. |
|
|
|||||||||||||||||||||
|
|
• RESETSTAT is driven low once the DVDD18 supply is available. |
|
|
|||||||||||||||||||||
|
|
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin |
|||||||||||||||||||||||
INFORMATION |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
t4a |
• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the |
||||||||||||||||||||||||
|
|||||||||||||||||||||||||
|
|
|
voltage for DVDD15 must never exceed DVDD18. |
|
|
||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||
|
t4b |
• |
|
|
may be driven high any time after DVDD18 is at a valid level. In a |
|
|
|
controlled boot, |
|
must be high before |
|
is driven |
||||||||||||
|
RESET |
POR- |
RESET |
POR |
|||||||||||||||||||||
|
|
|
high. |
|
|
||||||||||||||||||||
|
|
|
|
|
|
|
|||||||||||||||||||
|
t5 |
• |
|
must continue to remain low for at least 100 μs after power has stabilized. |
|
|
|||||||||||||||||||
|
POR |
|
|
||||||||||||||||||||||
|
|
End Power Stabilization Phase |
|
|
|||||||||||||||||||||
|
|
|
|||||||||||||||||||||||
|
t6 |
• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay |
|||||||||||||||||||||||
|
|
|
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs. |
|
|
||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|||||||||||||||||
|
t7 |
• |
|
|
|
must be held low for at least 24 transitions of the REFCLK after |
|
|
|
has stabilized at a high level. |
|
|
|||||||||||||
|
RESETFULL |
POR |
|
|
|||||||||||||||||||||
|
t8 |
• The rising edge of the |
|
will remove the reset to the efuse farm allowing the scan to begin. |
|
|
|||||||||||||||||||
|
RESETFULL |
|
|
||||||||||||||||||||||
|
|
• Once device initialization and the efuse farm scan are complete, the |
|
signal is driven high. This delay will be 10000 to 50000 |
|||||||||||||||||||||
|
|
RESETSTAT |
|||||||||||||||||||||||
|
|
|
clock cycles. |
|
|
||||||||||||||||||||
|
|
End Device Initialization Phase |
|
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|||||||||||||||||
|
t9 |
• GPIO configuration bits must be valid for at least 12 transitions of the REFCLK before the rising edge of |
|
|
|
|
|
|
|||||||||||||||||
|
RESETFULL |
|
|
||||||||||||||||||||||
|
t10 |
• GPIO configuration bits must be held valid for at least 12 transitions of the REFCLK after the rising edge of |
|
|
|
|
|
||||||||||||||||||
|
RESETFULL |
|
|
||||||||||||||||||||||
|
End of Table 7-3 |
|
|
||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
98 |
Copyright 2011 Texas Instruments Incorporated |