- •Release History
- •Contents
- •List of Figures
- •List of Tables
- •1 TMS320TCI6618 Features
- •1.1 KeyStone Architecture
- •1.2 Device Description
- •1.3 Functional Block Diagram
- •2 Device Overview
- •2.1 Device Characteristics
- •2.2 CPU (DSP Core) Description
- •2.3 Memory Map Summary
- •2.4 Boot Sequence
- •2.5 Boot Modes Supported and PLL Settings
- •2.5.1 Boot Device Field
- •2.5.2 Device Configuration Field
- •2.5.2.1 No Boot Device Configuration
- •2.5.2.2 Serial Rapid I/O Boot Device Configuration
- •2.5.2.3 Ethernet (SGMII) Boot Device Configuration
- •2.5.2.4 PCI Boot Device Configuration
- •2.5.2.5 I2C Boot Device Configuration
- •2.5.2.6 SPI Boot Device Configuration
- •2.5.2.7 HyperLink Boot Device Configuration
- •2.5.3 PLL Settings
- •2.6 Second-Level Bootloaders
- •2.7 Terminals
- •2.8 Terminal Functions
- •2.9 Development
- •2.9.1 Development Support
- •2.9.2 Device Support
- •Related Documentation from Texas Instruments
- •3 Device Configuration
- •3.1 Device Configuration at Device Reset
- •3.2 Peripheral Selection After Device Reset
- •3.3 Device State Control Registers
- •3.3.1 Device Status (DEVSTAT) Register
- •3.3.2 Device Configuration Register
- •3.3.3 JTAG ID (JTAGID) Register Description
- •3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
- •3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
- •3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
- •3.3.7 Reset Status (RESET_STAT) Register
- •3.3.8 Reset Status Clear (RESET_STAT_CLR) Register
- •3.3.9 Boot Complete (BOOTCOMPLETE) Register
- •3.3.10 Power State Control (PWRSTATECTL) Register
- •3.3.11 NMI Even Generation to CorePac (NMIGRx) Register
- •3.3.12 IPC Generation (IPCGRx) Registers
- •3.3.13 IPC Acknowledgement (IPCARx) Registers
- •3.3.14 IPC Generation Host (IPCGRH) Register
- •3.3.15 IPC Acknowledgement Host (IPCARH) Register
- •3.3.16 Timer Input Selection Register (TINPSEL)
- •3.3.17 Timer Output Selection Register (TOUTPSEL)
- •3.3.18 Reset Mux (RSTMUXx) Register
- •3.4 Pullup/Pulldown Resistors
- •4 System Interconnect
- •4.1 Internal Buses, Bridges, and Switch Fabrics
- •4.2 Data Switch Fabric Connections
- •4.3 Configuration Switch Fabric
- •4.4 Bus Priorities
- •5 C66x CorePac
- •5.1 Memory Architecture
- •5.1.1 L1P Memory
- •5.1.2 L1D Memory
- •5.1.3 L2 Memory
- •5.1.4 MSM SRAM
- •5.1.5 L3 Memory
- •5.2 Memory Protection
- •5.3 Bandwidth Management
- •5.4 Power-Down Control
- •5.5 CorePac Resets
- •5.6 CorePac Revision
- •5.7 C66x CorePac Register Descriptions
- •6 Device Operating Conditions
- •6.1 Absolute Maximum Ratings
- •6.2 Recommended Operating Conditions
- •6.3 Electrical Characteristics
- •7 TMS320TCI6618 Peripheral Information and Electrical Specifications
- •7.1 Parameter Information
- •7.1.1 1.8-V Signal Transition Levels
- •7.1.2 Timing Parameters and Board Routing Analysis
- •7.2 Recommended Clock and Control Signal Transition Behavior
- •7.3 Power Supplies
- •7.3.1 Power-Up Sequencing
- •7.3.1.1 Core-Before-IO Power Sequencing
- •7.3.1.2 IO-Before-Core Power Sequencing
- •7.3.1.3 Prolonged Resets
- •7.3.2 Power-Down Sequence
- •7.3.3 Power Supply Decoupling and Bulk Capacitors
- •7.3.4 SmartReflex
- •7.4 Enhanced Direct Memory Access (EDMA3) Controller
- •7.4.1 EDMA3 Device-Specific Information
- •7.4.2 EDMA3 Channel Synchronization Events
- •7.5 Interrupts
- •7.5.1 Interrupt Sources and Interrupt Controller
- •7.5.2 INTC Registers
- •7.5.2.1 INTC0 Register Map
- •7.5.2.2 INTC1 Register Map
- •7.5.2.3 INTC2 Register Map
- •7.5.3 Inter-Processor Register Map
- •7.5.4 NMI and LRESET
- •7.5.5 External Interrupts Electrical Data/Timing
- •7.6 Memory Protection Unit (MPU)
- •7.6.1 MPU Registers
- •7.6.1.1 MPU Register Map
- •7.6.1.2 Device-Specific MPU Registers
- •7.6.2 MPU Programmable Range Registers
- •7.6.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
- •7.6.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
- •7.6.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
- •7.7 Reset Controller
- •7.7.1 Power-on Reset
- •7.7.2 Hard Reset
- •7.7.3 Soft Reset
- •7.7.4 Local Reset
- •7.7.5 Reset Priority
- •7.7.6 Reset Controller Register
- •7.7.7 Reset Electrical Data/Timing
- •7.8 Main PLL and the PLL Controller
- •7.8.1 Main PLL Controller Device-Specific Information
- •7.8.1.1 Internal Clocks and Maximum Operating Frequencies
- •7.8.1.2 Main PLL Controller Operating Modes
- •7.8.1.3 Main PLL Stabilization, Lock, and Reset Times
- •7.8.2 PLL Controller Memory Map
- •7.8.2.1 PLL Secondary Control Register (SECCTL)
- •7.8.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
- •7.8.2.3 PLL Controller Clock Align Control Register (ALNCTL)
- •7.8.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
- •7.8.2.5 SYSCLK Status Register (SYSTAT)
- •7.8.2.6 Reset Type Status Register (RSTYPE)
- •7.8.2.7 Reset Control Register (RSTCTRL)
- •7.8.2.8 Reset Configuration Register (RSTCFG)
- •7.8.2.9 Reset Isolation Register (RSISO)
- •7.8.3 Main PLL Control Registers
- •7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
- •7.9.1 DDR3 PLL Control Register
- •7.9.2 DDR3 PLL Device-Specific Information
- •7.9.3 DDR3 PLL Input Clock Electrical Data/Timing
- •7.10 PASS PLL
- •7.10.1 PASS PLL Control Register
- •7.10.2 PASS PLL Device-Specific Information
- •7.10.3 PASS PLL Input Clock Electrical Data/Timing
- •7.11 DDR3 Memory Controller
- •7.11.1 DDR3 Memory Controller Device-Specific Information
- •7.11.2 DDR3 Memory Controller Electrical Data/Timing
- •7.12 I2C Peripheral
- •7.12.1 I2C Device-Specific Information
- •7.12.2 I2C Peripheral Register Description(s)
- •7.12.3 I2C Electrical Data/Timing
- •7.12.3.1 Inter-Integrated Circuits (I2C) Timing
- •7.13 SPI Peripheral
- •7.13.1 SPI Electrical Data/Timing
- •7.13.1.1 SPI Timing
- •7.14 HyperLink Peripheral
- •7.15 UART Peripheral
- •7.16 PCIe Peripheral
- •7.17 Packet Accelerator
- •7.18 Security Accelerator
- •7.19 Ethernet MAC (EMAC)
- •7.20 Management Data Input/Output (MDIO)
- •7.21 Timers
- •7.21.1 Timers Device-Specific Information
- •7.21.2 Timers Electrical Data/Timing
- •7.22 Rake Search Accelerator (RSA)
- •7.23 Enhanced Viterbi-Decoder Coprocessor (VCP2)
- •7.24 Third-Generation Turbo Decoder Coprocessor (TCP3d)
- •7.25 Turbo Encoder Coprocessor (TCP3e)
- •7.26 Bit Rate Coprocessor (BCP)
- •7.27 Serial RapidIO (SRIO) Port
- •7.28 General-Purpose Input/Output (GPIO)
- •7.28.1 GPIO Device-Specific Information
- •7.28.2 GPIO Electrical Data/Timing
- •7.29 Semaphore2
- •7.30 Antenna Interface Subsystem 2
- •7.33 FFTC
- •7.34 Emulation Features and Capability
- •7.34.1 Advanced Event Triggering (AET)
- •7.34.2 Trace
- •7.34.2.1 Trace Electrical Data/Timing
- •7.34.3 IEEE 1149.1 JTAG
- •7.34.3.1 IEEE 1149.1 JTAG Compatibility Statement
- •7.34.3.2 JTAG Electrical Data/Timing
- •8 Mechanical Data
- •8.1 Packaging Information
- •8.2 Package CYP
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TMS320TCI6618 |
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Communications Infrastructure KeyStone SoC |
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SPRS688—February 2011 |
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Table 7-65 |
I2C Registers (Part 2 of 2) |
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Hex Address Range |
Acronym |
Register Name |
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0253 0034 |
ICPID1 |
I2C peripheral identification register 1 [Value: 0x0000 0105] |
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0253 0038 |
ICPID2 |
I2C peripheral identification register 2 [Value: 0x0000 0005] |
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0253 003C -0253 007F |
- |
Reserved |
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End of Table 7-65 |
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7.12.3 I2C Electrical Data/Timing
7.12.3.1 Inter-Integrated Circuits (I2C) Timing
Table 7-66 I2C Timing Requirements (1)
(see Figure 7-38)
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Standard Mode |
Fast Mode |
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No. |
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Min |
Max |
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Max |
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1 |
tc(SCL) |
Cycle time, SCL |
10 |
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2 |
tsu(SCLH-SDAL) |
Setup time, SCL high before SDA low (for a repeated START |
4.7 |
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0.6 |
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3 |
th(SDAL-SCLL) |
Hold time, SCL low after SDA low (for a START and a repeated |
4 |
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START condition) |
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4 |
tw(SCLL) |
Pulse duration, SCL low |
4.7 |
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5 |
tw(SCLH) |
Pulse duration, SCL high |
4 |
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6 |
tsu(SDAV-SCLH) |
Setup time, SDA valid before SCL high |
250 |
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7 |
th(SCLL-SDAV) |
Hold time, SDA valid after SCL low (for I2C bus devices) |
0 (3) |
3.45 |
0 (3) |
0.9 (4) |
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8 |
tw(SDAH) |
Pulse duration, SDA high between STOP and START conditions |
4.7 |
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1.3 |
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9 |
t |
r(SDA) |
Rise time, SDA |
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1000 |
20 + 0.1C |
(5) |
300 |
ns |
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b |
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10 |
t |
r(SCL) |
Rise time, SCL |
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1000 |
20 + 0.1C |
(5) |
300 |
ns |
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b |
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11 |
tf(SDA) |
Fall time, SDA |
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300 |
20 + 0.1Cb |
(5) |
300 |
ns |
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12 |
tf(SCL) |
Fall time, SCL |
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300 |
20 + 0.1Cb |
(5) |
300 |
ns |
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13 |
tsu(SCLH-SDAH) |
Setup time, SCL high before SDA high (for STOP condition) |
4 |
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14 |
tw(SP) |
Pulse duration, spike (must be suppressed) |
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50 |
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Cb (5) |
Capacitive load for each bus line |
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pF |
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End of Table 7-66
1 The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down
2 A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH) ≥250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
4 The maximum th(SDA-SCLL) has to be met only if the device does not stretch the low period [tw(SCLL)] of the SCL signal. 5 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
ADVANCE INFORMATION
Copyright 2011 Texas Instruments Incorporated |
175 |
INFORMATION ADVANCE
TMS320TCI6618 |
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SPRS688—February 2011 |
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Figure 7-38 |
I2C Receive Timings |
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SCL |
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10 |
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5 |
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13 |
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1 |
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3 |
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3 |
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7 |
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2 |
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Stop |
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Start |
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Repeated |
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Stop |
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Start |
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||||||||||
Table 7-67 |
I2C Switching Characteristics (1) |
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(see Figure 7-39) |
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Standard Mode |
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Fast Mode |
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No. |
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Parameter |
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Min |
Max |
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Min |
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Max |
Unit |
||||||||||||||||||||||||||||||||||||
16 |
tc(SCL) |
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Cycle time, SCL |
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10 |
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2.5 |
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ms |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
17 |
tsu(SCLH-SDAL) |
|
Setup time, SCL high to SDA low (for a repeated START condition) |
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4.7 |
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0.6 |
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ms |
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18 |
th(SDAL-SCLL) |
|
Hold time, SDA low after SCL low (for a START and a repeated START |
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4 |
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0.6 |
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ms |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
condition) |
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19 |
tw(SCLL) |
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|
Pulse duration, SCL low |
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4.7 |
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1.3 |
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ms |
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20 |
tw(SCLH) |
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|
Pulse duration, SCL high |
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4 |
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0.6 |
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ms |
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21 |
td(SDAV-SDLH) |
|
Delay time, SDA valid to SCL high |
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250 |
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100 |
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ns |
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22 |
tv(SDLL-SDAV) |
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Valid time, SDA valid after SCL low (for I2C bus devices) |
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0 |
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0 |
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0.9 |
ms |
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23 |
tw(SDAH) |
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Pulse duration, SDA high between STOP and START conditions |
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4.7 |
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1.3 |
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ms |
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24 |
tr(SDA) |
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Rise time, SDA |
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1000 |
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20 + 0.1Cb |
(1) |
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300 |
ns |
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25 |
tr(SCL) |
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Rise time, SCL |
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1000 |
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20 + 0.1Cb |
(1) |
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300 |
ns |
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26 |
tf(SDA) |
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Fall time, SDA |
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300 |
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20 + 0.1Cb |
(1) |
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300 |
ns |
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27 |
tf(SCL) |
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Fall time, SCL |
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300 |
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20 + 0.1Cb |
(1) |
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300 |
ns |
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28 |
td(SCLH-SDAH) |
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Delay time, SCL high to SDA high (for STOP condition) |
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4 |
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0.6 |
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ms |
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Cp |
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Capacitance for each I2C pin |
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10 |
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10 |
pF |
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End of Table 7-67 |
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1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
176 |
Copyright 2011 Texas Instruments Incorporated |
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|
TMS320TCI6618 |
|
|
Communications Infrastructure KeyStone SoC |
|
www.ti.com |
|
|
SPRS688—February 2011 |
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|
Figure 7-39 I2C Transmit Timings |
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26 |
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24 |
SDA |
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23 |
21 |
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19 |
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25 |
20 |
28 |
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SCL |
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16 |
27 |
18 |
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22 |
17 |
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18 |
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Stop |
Start |
Repeated |
Stop |
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Start |
|
ADVANCE INFORMATION
Copyright 2011 Texas Instruments Incorporated |
177 |