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INFORMATION ADVANCE

TMS320TCI6618

Communications Infrastructure KeyStone SoC

SPRS688—February 2011

www.ti.com

 

7.13 SPI Peripheral

The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on TCI6618 is supported only in Master mode. Additional chip-level components can also be included, such as temperature sensors or an I/O expander.

7.13.1 SPI Electrical Data/Timing

7.13.1.1 SPI Timing

Table 7-68 SPI Timing Requirements

See Figure 7-40)

No.

 

 

Min

Max

Unit

 

 

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

 

 

 

 

 

 

 

 

 

7

tsu(SOMI-SPC)

Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 0

2

 

ns

 

 

 

 

 

 

7

tsu(SOMI-SPC)

Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 0 Phase = 1

2

 

ns

 

 

 

 

 

 

7

tsu(SOMI-SPC)

Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 0

2

 

ns

 

 

 

 

 

 

7

tsu(SOMI-SPC)

Input Setup Time, SPIx_SOMI valid before receive edge of SPIx_CLk. Polarity = 1 Phase = 1

2

 

ns

 

 

 

 

 

 

8

th(SPC-SOMI)

Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 0

5

 

ns

 

 

 

 

 

 

8

th(SPC-SOMI)

Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 0 Phase = 1

5

 

ns

 

 

 

 

 

 

8

th(SPC-SOMI)

Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 0

5

 

ns

 

 

 

 

 

 

8

th(SPC-SOMI)

Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK. Polarity = 1 Phase = 1

5

 

ns

 

 

 

 

 

 

End of Table 7-68

 

 

 

 

 

 

 

 

 

 

Table 7-69

SPI Switching Characteristics (Part 1 of 2)

 

 

 

(See Figure 7-40 and Figure 7-41)

 

 

 

 

 

 

 

 

 

 

No.

 

 

Parameter

Min

Max

Unit

 

 

 

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

 

 

 

 

 

 

 

 

 

1

tc(SPC)

 

Cycle Time, SPIx_CLK, All Master Modes

1/66MHz

 

ns

 

 

 

 

 

 

 

2

tw(SPCH)

 

Pulse Width High, SPIx_CLK, All Master Modes

7

 

ns

 

 

 

 

 

 

 

3

tw(SPCL)

 

Pulse Width Low, SPIx_CLK, All Master Modes

7

 

ns

 

 

 

 

 

 

4

td(SIMO-SPC)

Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.

 

5

ns

 

 

 

Polarity = 0, Phase = 0.

 

 

 

 

 

 

 

 

 

4

td(SIMO-SPC)

Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK.

 

5

ns

 

 

 

Polarity = 0, Phase = 1.

 

 

 

 

 

 

 

 

 

4

td(SIMO-SPC)

Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK

 

5

ns

 

 

 

Polarity = 1, Phase = 0

 

 

 

 

 

 

 

 

 

4

td(SIMO-SPC)

Setup (Delay), initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK

 

5

ns

 

 

 

Polarity = 1, Phase = 1

 

 

 

 

 

 

 

 

 

5

td(SPC-SIMO)

Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on

 

5

ns

 

 

 

SPIx_CLK. Polarity = 0 Phase = 0

 

 

 

 

 

 

 

 

 

5

td(SPC-SIMO)

Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on

 

5

ns

 

 

 

SPIx_CLK Polarity = 0 Phase = 1

 

 

 

 

 

 

 

 

 

5

td(SPC-SIMO)

Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on

 

5

ns

 

 

 

SPIx_CLK Polarity = 1 Phase = 0

 

 

 

 

 

 

 

 

 

5

td(SPC-SIMO)

Setup (Delay), subsequent data bits valid on SPIx_SIMO to initial edge on

 

5

ns

 

 

 

SPIx_CLK Polarity = 1 Phase = 1

 

 

 

 

 

 

 

 

 

6

toh(SPC-SIMO)

Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for

0.5*tc - 2

 

ns

 

 

 

final bit. Polarity = 0 Phase = 0

 

 

 

 

 

 

 

 

 

6

toh(SPC-SIMO)

Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for

0.5*tc - 2

 

ns

 

 

 

final bit. Polarity = 0 Phase = 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

178

 

 

Copyright 2011 Texas Instruments Incorporated

 

 

 

 

 

TMS320TCI6618

 

 

 

 

Communications Infrastructure KeyStone SoC

 

www.ti.com

 

 

 

SPRS688—February 2011

 

 

 

 

 

 

 

Table 7-69

SPI Switching Characteristics (Part 2 of 2)

 

 

 

 

(See Figure 7-40 and Figure 7-41)

 

 

 

 

 

 

 

 

 

 

 

 

No.

 

 

Parameter

Min

Max

Unit

 

6

toh(SPC-SIMO)

Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for

0.5*tc - 2

 

ns

 

 

 

 

final bit. Polarity = 1 Phase = 0

 

 

 

 

 

 

 

 

 

 

 

6

toh(SPC-SIMO)

Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for

0.5*tc - 2

 

ns

 

 

 

 

final bit. Polarity = 1 Phase = 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Additional SPI Master Timings — 4 Pin Mode with Chip Select Option

 

 

 

 

 

 

 

 

 

 

19

td(SCS-SPC)

Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 0

2*P2 - 5

2*P2 + 5

ns

 

 

 

 

 

 

 

 

19

td(SCS-SPC)

Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 1

0.5*tc + (2*P2) - 5

0.5*tc + (2*P2) + 5

ns

 

 

 

 

 

 

 

 

19

td(SCS-SPC)

Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 0

2*P2 - 5

2*P2 + 5

ns

INFORMATION

 

 

 

 

 

 

 

19

td(SCS-SPC)

Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 1

0.5*tc + (2*P2) - 5

0.5*tc + (2*P2) + 5

ns

 

 

 

 

 

 

 

 

20

td(SPC-SCS)

Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0

1*P2 - 5

1*P2 + 5

ns

 

 

 

 

Phase = 0

 

 

 

 

 

 

 

 

 

 

 

20

td(SPC-SCS)

Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0

0.5*tc + (1*P2) - 5

0.5*tc + (1*P2) + 5

ns

 

 

 

 

Phase = 1

 

 

 

 

 

 

 

 

 

 

 

20

td(SPC-SCS)

Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1

1*P2 - 5

1*P2 + 5

ns

 

 

 

 

Phase = 0

 

 

 

 

 

 

 

 

 

 

 

20

td(SPC-SCS)

Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1

0.5*tc + (1*P2) - 5

0.5*tc + (1*P2) + 5

ns

 

 

 

 

Phase = 1

 

 

 

 

 

 

 

 

 

 

 

 

 

tw(SCSH)

 

Minimum inactive time on SPIx_SCS\ pin between two transfers when

2*P2 - 5

 

ns

 

 

 

 

SPIx_SCS\ is not held using the CSHOLD feature.

 

 

 

 

 

 

 

 

 

 

ADVANCE

End of Table 7-69

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Copyright 2011 Texas Instruments Incorporated

179

INFORMATION ADVANCE

TMS320TCI6618

 

 

 

 

 

 

 

Communications Infrastructure KeyStone SoC

 

 

 

 

 

SPRS688—February 2011

 

 

 

 

 

 

www.ti.com

 

 

 

 

 

 

 

 

Figure 7-40

SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode

 

 

 

 

 

1

 

 

 

MASTER MODE

 

 

 

2

3

 

 

POLARITY = 0 PHASE = 0

 

 

 

 

 

 

 

 

SPIx_CLK

 

 

 

 

 

 

 

 

 

4

 

 

5

 

6

 

SPIx_SIMO

 

MO(0)

 

MO(1)

 

MO(n-1)

MO(n)

 

 

 

7

8

 

 

 

 

SPIx_SOMI

 

MI(0)

 

MI(1)

 

MI(n-1)

MI(n)

 

 

 

 

 

 

 

MASTER MODE

 

 

4

 

 

 

 

POLARITY = 0 PHASE = 1

 

 

 

 

 

 

 

 

 

SPIx_CLK

 

 

 

 

 

 

 

 

 

 

 

5

6

 

 

 

SPIx_SIMO

MO(0)

 

MO(1)

 

MO(n-1)

MO(n)

 

 

7

8

 

 

 

 

 

SPIx_SOMI

MI(0)

 

MI(1)

 

MI(n-1)

MI(n)

 

 

4

 

 

 

 

MASTER MODE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

POLARITY = 1 PHASE = 0

 

SPIx_CLK

 

 

 

 

 

 

 

 

 

 

 

5

 

 

6

 

SPIx_SIMO

 

MO(0)

 

MO(1)

 

MO(n-1)

MO(n)

 

 

 

7

8

 

 

 

 

SPIx_SOMI

 

MI(0)

 

MI(1)

 

MI(n-1)

MI(n)

 

 

 

 

 

 

 

MASTER MODE

 

 

 

 

 

 

 

POLARITY = 1 PHASE = 1

 

SPIx_CLK

 

 

 

 

 

 

 

 

 

4

 

5

6

 

 

 

SPIx_SIMO

MO(0)

 

MO(1)

 

MO(n-1)

MO(n)

 

 

7

8

 

 

 

 

 

SPIx_SOMI

MI(0)

MI(1)

 

MI(n-1)

 

MI(n)

Figure 7-41

SPI Additional Timings for 4-Pin Master Mode with Chip Select Option

 

 

 

 

MASTER MODE 4 PIN WITH CHIP SELECT

 

 

 

 

19

 

 

 

20

 

 

SPIx_CLK

 

 

 

 

 

 

 

SPIx_SIMO

MO(0)

MO(1)

MO(n-1)

MO(n)

 

SPIx_SOMI

 

MI(0)

MI(1)

MI(n-1)

MI(n)

 

 

SPIx_SCS

 

 

 

 

 

 

 

180

Copyright 2011 Texas Instruments Incorporated
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