7.8.2 PLL Controller Memory Map

7.8.1.2 Main PLL Controller Operating Modes

7.8.1.3 Main PLL Stabilization, Lock, and Reset Times

7.8.2.1 PLL Secondary Control Register (SECCTL)

7.8.2.3 PLL Controller Clock Align Control Register (ALNCTL)

7.8.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)

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TMS320TCI6618

Communications Infrastructure KeyStone SoC

www.ti.com	SPRS688—February 2011

Note—In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8 (SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the system.

The Main PLL controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, REFCLK is generated from the PLL output using the divider POSTDIV and the PLL multiplier PLLM. In bypass mode, PLL output is fed directly to REFCLK.

All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed.

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup. The PLL should not be operated until this stabilization time has expired.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value, see Table 7-47.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main PLL lock time is given in Table 7-47.

Table 7-47	Main PLL Stabilization, Lock, and Reset Times

		Min	Typ	Max	Unit
PLL stabilization time		100			μs

PLL lock time				2000 × C (1)
PLL reset time		1000			ns

End of Table 7-47

1 C = SYSCLK(N|P) cycle time in ns.

The memory map of the PLL controller is shown in Table 7-48. TMS320TCI6618 specific PLL Controller register definitions can be found in the sections following the Table 7-48, for other registers in the table, see the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59.

CAUTION—Note that only registers documented here are accessible on the TMS320TCI6618. Other addresses in the PLL controller memory map including the reserved registers should not be modified. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits. It is recommended to use read-modify-write sequence to make any changes to the valid bits in the register.

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	Communications Infrastructure KeyStone SoC
	SPRS688—February 2011			www.ti.com
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	Table 7-48	PLL Controller Registers (Including Reset Controller)

	Hex Address Range		Acronym	Register Name
	0231 0000 - 0231 00E3		-	Reserved

	0231 00E4		RSTYPE	Reset Type Status Register (Reset Controller)

	0231 00E8		RSTCTRL	Software Reset Control Register (Reset Controller)

	0231 00EC		RSTCFG	Reset Configuration Register (Reset Controller)

	0231 00F0		RSISO	Reset isolation register (Reset Controller)

	0231 00F0 - 0231 00FF		-	Reserved
ADVANCE
	0231 0100		PLLCTL	PLL Control Register

	0231 0118		PLLDIV1	Reserved
	0231 0104		-	Reserved
	0231 0108		SECCTL	PLL Secondary Control Register
	0231 010C		-	Reserved
	0231 0110		PLLM	PLL Multiplier Control Register

	0231 0114		PREDIV	PLL pre-divider control register
INFORMATION

	0231 011C		PLLDIV2	PLL controller divider 2 register
	0231 011C		PLLDIV2	PLL controller divider 2 register

	0231 0120		PLLDIV3	Reserved

	0231 0124		-	Reserved

	0231 0128		POSTDIV	PLL Post-Divider Register

	0231 012C - 0231 0134		-	Reserved

	0231 0138		PLLCMD	PLL Controller Command Register

	0231 013C		PLLSTAT	PLL Controller Status Register

	0231 0140		ALNCTL	PLL Controller Clock Align Control Register

	0231 0144		DCHANGE	PLLDIV Ratio Change Status Register

	0231 0148		CKEN	Reserved

	0231 014C		CKSTAT	Reserved

	0231 0150		SYSTAT	SYSCLK Status Register

	0231 0154 - 0231 015C		-	Reserved

	0231 0160		PLLDIV4	Reserved

	0231 0164		PLLDIV5	PLL Controller Divider 5 Register

	0231 0168		PLLDIV6	Reserved

	0231 016C		PLLDIV7	Reserved

	0231 0170		PLLDIV8	PLL Controller Divider 8 Register

	0231 0174 - 0231 0193		PLLDIV9 - PLLDIV16	Reserved

	0231 0194 - 0231 01FF		-	Reserved

	End of Table 7-48

158	Copyright 2011 Texas Instruments Incorporated

TMS320TCI6618

Communications Infrastructure KeyStone SoC

www.ti.com	SPRS688—February 2011

The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 7-18 and described in Table 7-49.

Figure 7-18 PLL Secondary Control Register (SECCTL))

Table 7-49		PLL Secondary Control Register (SECCTL) Field Descriptions

Bit	Field		Description
31-24	Reserved		Reserved

23	BYPASS		Main PLL Bypass Enable
			0 = Main PLL Bypass disabled
			1 = Main PLL Bypass enabled

22-19	OUTPUT_DIVIDE		Output Divider ratio bits.
			0h	= ÷1. Divide frequency by 1.
			1h	= ÷2. Divide frequency by 2.
			2h	= ÷3. Divide frequency by 3.
			3h	= ÷4. Divide frequency by 4.
			4h	- Fh = ÷5 to ÷16. Divide frequency by 5 to divide frequency by 80.

18-0	Reserved		Reserved

End of Table 7-49

7.8.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)

The PLL controller divider registers (PLLDIV2, PLLDIV5, PLLDIV8) are shown in Figure 7-19 and described in Table 7-50. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different and mentioned in the footnote of Figure 7-19.

Figure 7-19 PLL Controller Divider Register (PLLDIVn)

	31	16	15	14	8	7	0

	Reserved		Dn (1) EN	Reserved			RATIO
	R-0		R/W-1	R-0			R/W-n (2)
	Legend: R/W = Read/Write; R = Read only; -n = value after reset
1	D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8
2	n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8

Table 7-50		PLL Controller Divider Register (PLLDIVn) Field Descriptions

Bit	Field		Description
31-16	Reserved		Reserved.

15	DnEN		Divider Dn enable bit. (see footnote of Figure 7-19)
			0	= Divider n is disabled.
			1	= No clock output. Divider n is enabled.

159

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SPRS688—February 2011				www.ti.com
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Table 7-50		PLL Controller Divider Register (PLLDIVn) Field Descriptions

Bit	Field		Description
14-8	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

7-0	RATIO		Divider ratio bits. (see footnote of Figure 7-19)
			0h	= ÷1. Divide frequency by 1.
			1h	= ÷2. Divide frequency by 2.
			2h	= ÷3. Divide frequency by 3.
			3h	= ÷4. Divide frequency by 4.
			4h	- 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.

End of Table 7-50

The PLL controller clock align control register (ALNCTL) is shown in Figure 7-20 and described in Table 7-51.

Figure 7-20 PLL Controller Clock Align Control Register (ALNCTL)

31	8	7	6	5	4	3	2	1	0

Reserved		ALN8	Reserved		ALN5	Reserved		ALN2	Reserved

R-0		R/W-1		R-0	R/W-1		R-0	R/W-1	R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

Table 7-51		PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Bit	Field		Description
31-8
6-5	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
3-2	Reserved
3-2
0

7	ALN8		SYSCLKn alignment. Do not change the default values of these fields.
4	ALN5		0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new
4	ALN5		ratio immediately after the GOSET bit in PLLCMD is set.
1	ALN2		ratio immediately after the GOSET bit in PLLCMD is set.
1	ALN2		1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.

			The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.

End of Table 7-51

OUTPUT_DIVIDE

R-0000 0000

RW-001 0000 0000 0000 0000

Legend: R/W = Read/Write; R = Read only; -n = value after reset

Whenever a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE status register. During the GO operation, the PLL controller will change only the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other clocks. The PLLDIV divider ratio change status register is shown in Figure 7-21 and described in Table 7-52.

Figure 7-21 PLLDIV Divider Ratio Change Status Register (DCHANGE)

31	8	7	6	5	4	3	2	1	0

Reserved		SYS8	Reserved		SYS5	Reserved		SYS2	Reserved

R-0		R/W-0		R-0	R/W-0		R-0	R/W-0	R-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

160	Copyright 2011 Texas Instruments Incorporated