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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320tci6618.pdf

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TMS320TCI6618

Communications Infrastructure KeyStone SoC

www.ti.com	SPRS688—February 2011

7.9.2 DDR3 PLL Device-Specific Information

As shown in Figure 7-31, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3 PLL are affected as described in Section 7.7 ‘‘Reset Controller’’ on page 149. DDR3 PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

7.9.3 DDR3 PLL Input Clock Electrical Data/Timing

Table 7-62 DDR3 PLL DDRREFCLK(N|P) Timing Requirements

(see Figure 7-33 and Figure 7-30)

No.			Min	Max	Unit	INFORMATION
No.			Min	Max	Unit
		DDRCLK[P:N]

1	tc(DDRCLKN)	Cycle Time _ DDRCLKN cycle time	3.2	25	ns

1	tc(DDRCLKP)	Cycle Time _ DDRCLKP cycle time	3.2	25	ns

3	tw(DDRCLKN)	Pulse Width _ DDRCLKN high	0.45*tc(DDRCLKN)	0.55*tc(DDRCLKN)	ns

2	tw(DDRCLKN)	Pulse Width _ DDRCLKN low	0.45*tc(DDRCLKN)	0.55*tc(DDRCLKN)	ns

2	tw(DDRCLKP)	Pulse Width _ DDRCLKP high	0.45*tc(DDRCLKP)	0.55*tc(DDRCLKP)	ns

3	tw(DDRCLKP)	Pulse Width _ DDRCLKP low	0.45*tc(DDRCLKP)	0.55*tc(DDRCLKP)	ns

4	tr(DDRCLKN_250mv)	Transition Time _ DDRCLKN Rise time (250mV)	50	350	ps
						ADVANCE
4	tf(DDRCLKN_250mv)	Transition Time _ DDRCLKN Fall time (250mV)	50	350	ps

4	tr(DDRCLKP_250mv)	Transition Time _ DDRCLKP Rise time (250mV)	50	350	ps
4	tr(DDRCLKP_250mv)	Transition Time _ DDRCLKP Rise time (250mV)	50	350	ps

4	tf(DDRCLKP_250mv)	Transition Time _ DDRCLKP Fall time (250mV)	50	350	ps

5	tj(DDRCLKN)	Jitter, Peak_to_Peak _ Periodic DDRCLKN		0.025*tc(DDRCLKN)	ps

5	tj(DDRCLKP)	Jitter, Peak_to_Peak _ Periodic DDRCLKP		0.025*tc(DDRCLKN)	ps

End of Table 7-62

Figure 7-33 DDR3 PLL DDRCLK Timing

2 3

DDRCLKN

DDRCLKP

7.10 PASS PLL

The PASS PLL generates interface clocks for the Packet Accelerator Subsystem. Using the PACLKSEL pin the user can select the input source of PASS PLL as either the output of Main PLL mux or the PASSCLK clock reference sources. When coming out of power-on reset, PASS PLL comes out in a bypass mode and needs to be programmed to a valid frequency before being enabled and used.

PASS PLL power is supplied externally via the Main PLL power-supply pin (AVDDA3). An external EMI filter circuit must be added to all PLL supplies. Please see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 59 for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

169

INFORMATION ADVANCE

TMS320TCI6618
Communications Infrastructure KeyStone SoC
SPRS688—February 2011		www.ti.com
		www.ti.com
Figure 7-34 PASS PLL Block Diagram
SYSCLK(P\|N)	REFCLK	Main PLL and
	REFCLK	Main PLL and
ALTCORECLK(P\|N)		PLL Controller
ALTCORECLK(P\|N)
CORECLKSEL
PASS PLL		/2
PASS PLL	PLLOUT	Packet
	PLLOUT	Packet
PASSCLK(P\|N)		Accelerator
xPLLM
PACLKSEL

7.10.1 PASS PLL Control Register

The PASS PLL, which is used to drive the packet accelerator sub-system, does not use a PLL controller. PASS PLL can be controlled using the PAPLLCTL register located in Bootcfg module. This MMR exists inside the Bootcfg space. To write to this register, software should go through an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.5.3 ‘‘PLL Settings’’ on page 33. See 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 65 for the address location of the registers and locking and unlocking sequences for accessing the registers. This register is reset on POR only.

.	PASS PLL Control Register (PASSPLLCTL) (1)
Figure 7-35	PASS PLL Control Register (PASSPLLCTL) (1)
31		24	23	22	19	18	6	5	0

BWADJ[7:0]			BYPASS	Reserved		PLLM			PLLD

RW,+0000 1001			RW,+0	RW,+0001		RW,+0000000010011		RW,+000000

Legend: RW = Read/Write; -n = value after reset

1 This register is Reset on POR only. The regreset, reset, and bgreset from PLL are all tied to a common pll0_ctrl_rst_n. The pwrdn, regpwrdn, and bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.

Table 7-63		PASS PLL Control Register Field Descriptions

Bit	Field		Description
31-24	BWADJ[7:0]		BWADJ should be programmed to a value equal to half of PLLM[12:0]. Example: PLLM = 15, then BWADJ = 7

23	BYPASS		Enable Bypass Mode
			0 = Bypass Disabled
			1 = Bypass Enabled

22-19	Reserved		Reserved

18-6	PLLM		A 13-bit bus that selects the values for the multiplication factor (see Note below)

5-0	PLLD		A 6-bit bus that selects the values for the reference divider

End of Table 7-63

7.10.2 PASS PLL Device-Specific Information

As shown in Figure 7-34, the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Packet Accelerator Sub-System. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks of the PASS PLL are affected as described in Section 7.7 ‘‘Reset Controller’’ on page 149. PASS PLL is unlocked only during the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

170	Copyright 2011 Texas Instruments Incorporated

					TMS320TCI6618
			Communications Infrastructure KeyStone SoC
www.ti.com					SPRS688—February 2011
www.ti.com
7.10.3 PASS PLL Input Clock Electrical Data/Timing
Table 7-64		PASS PLL Timing Requirements
(See Figure 7-36 and Figure 7-30)

No.			Parameter	Min	Max	Unit
			PASSCLK[P:N]

1	tc(PASSCLKN)		Cycle Time _ PASSCLKN cycle time	3.2	25	ns

1	tc(PASSCLKP)		Cycle Time _ PASSCLKP cycle time	3.2	25	ns

3	tw(PASSCLKN)		Pulse Width _ PASSCLKN high	0.45*tc(PASSCLKN)	0.55*tc(PASSCLKN)	ns

2	tw(PASSCLKN)		Pulse Width _ PASSCLKN low	0.45*tc(PASSCLKN)	0.55*tc(PASSCLKN)	ns

2	tw(PASSCLKP)		Pulse Width _ PASSCLKP high	0.45*tc(PASSCLKP)	0.55*tc(PASSCLKP)	ns

3	tw(PASSCLKP)		Pulse Width _ PASSCLKP low	0.45*tc(PASSCLKP)	0.55*tc(PASSCLKP)	ns

4	tr(PASSCLKN_250mv)		Transition Time _ PASSCLKN Rise time (250 mV)	50	350	ps

4	tf(PASSCLKN_250mv)		Transition Time _ PASSCLKN Fall time (250 mV)	50	350	ps

4	tr(PASSCLKP_250mv)		Transition Time _ PASSCLKP Rise time (250 mV)	50	350	ps

4	tf(PASSCLKP_250mv)		Transition Time _ PASSCLKP Fall time (250 mV)	50	350	ps

5	tj(PASSCLKN)		Jitter, Peak_to_Peak _ Periodic PASSCLKN		100	ps, pk-pk

5	tj(PASSCLKP)		Jitter, Peak_to_Peak _ Periodic PASSCLKP		100	ps, pk-pk