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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320tci6618.pdf

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INFORMATION ADVANCE

TMS320TCI6618
Communications Infrastructure KeyStone SoC
SPRS688—February 2011				www.ti.com
				www.ti.com
Table 7-57		Reset Isolation Register (RSISO) Field Descriptions

Bit	Acronym		Description
31-10	Reserved		Reserved.

9	SRIOISO		Isolate SRIO module
			0	= Not reset isolated
			1	= Reset Isolated

8	SRISO		Isolate SmartReflex
			0	= Not reset isolated
			1	= Reset Isolated

7-4	Reserved		Reserved.

3	AIF2ISO		Isolate AIF2 module
			0	= Not reset isolated
			1	= Reset isolated

2-0	Reserved		Reserved.

End of Table 7-57

7.8.3 Main PLL Control Registers

The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the PLL controller for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software should go through an un-locking sequence using KICK0/KICK1 registers. For valid configurable values into the MAINPLLCTL register see Section 2.5.3 ‘‘PLL Settings’’ on page 33. See 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 65 for the address location of the registers and locking and unlocking sequences for accessing the registers. These registers reset only on a POR reset. See Figure 7-27 and Table 7-58 for MAINPLLCTL0 details and Figure 7-28 and Table 7-59 for MAINPLLCTL1 details.

Figure 7-27 Main PLL Control Register (MAINPLLCTL0)

31	24	23	19	18	12	11	6	5	0
BWADJ[7:0]		Reserved		PLLM[12:6]		Reserved			PLLD

RW,+0000 0101		RW - 0000 0		RW,+0000000		RW, +000000		RW,+000000
Legend: RW = Read/Write; -n = value after reset

Table 7-58		Main PLL Control Register (MAINPLLCTL0) Field Descriptions

Bit	Field		Description
31-24	BWADJ[7:0]		BWADJ should be programmed to a value equal to half of PLLM[12:0]. Example: PLLM = 15, then BWADJ = 7

23-19	Reserved		Reserved

18-12	PLLM[12:6]		A 13-bit bus that selects the values for the multiplication factor (see Note below)

11-6	Reserved		Reserved

5-0	PLLD		A 6-bit bus that selects the values for the reference divider

End of Table 7-58

Figure 7-28	Main PLL Control Register (MAINPLLCTL1)
31		7	6	5	0

	Reserved		ENSAT	Reserved

	RW - 0000000000000000000000000		RW - 0	RW000000
Legend: RW = Read/Write; -n = value after reset

164	Copyright 2011 Texas Instruments Incorporated

		TMS320TCI6618
		Communications Infrastructure KeyStone SoC
www.ti.com		SPRS688—February 2011
www.ti.com
Table 7-59 Main PLL Control Register (MAINPLLCTL1) Field Descriptions

Bit	Field	Description
31-7	Reserved	Reserved

6	ENSAT	Needs to be set to ‘1’ for proper operation of Main PLL

5-0	Reserved	Reserved

End of Table 7-59

Note—PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are controlled by the above chip level register. MAINPLLCTL0 register PLLM[12:6] bits should be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59 for the recommended programming sequence. Output Divide ratio and Bypass enable/disable of the Main PLL is also controlled by the SECCTL register in the PLL Controller. See the Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 59 for more details.

7.8.4 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing

Table 7-60		Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 1 of 3)
(see Figure 7-29 and Figure 7-30)

No.				Min	Max	Unit
			SYSCLK[P:N]

1	tc(SYSCLKN)		Cycle Time _ SYSCLKN cycle time	3.25 or 6.51 or 8.138 (2)		ns
1	tc(SYSCLKP)		Cycle Time _ SYSCLKP cycle time	3.25 or 6.51 or 8.138		ns

3	tw(SYSCLKN)		Pulse Width _ SYSCLKN high	0.45*tc	0.55*tc	ns

2	tw(SYSCLKN)		Pulse Width _ SYSCLKN low	0.45*tc	0.55*tc	ns

2	tw(SYSCLKP)		Pulse Width _ SYSCLKP high	0.45*tc	0.55*tc	ns

3	tw(SYSCLKP)		Pulse Width _ SYSCLKP low	0.45*tc	0.55*tc	ns

4	tr(SYSCLKN_250mv)		Transition Time _ SYSCLKN Rise time (250mV)	50	350	ps

4	tf(SYSCLKN_250mv)		Transition Time _ SYSCLKN Fall time (250mV)	50	350	ps

4	tr(SYSCLKP_250mv)		Transition Time _ SYSCLKP Rise time (250mV)	50	350	ps

4	tf(SYSCLKP_250mv)		Transition Time _ SYSCLKP Fall time (250mV)	50	350	ps

5	tj(SYSCLKN)		Jitter, Peak_to_Peak _ Periodic SYSCLKN		100	ps

5	tj(SYSCLKP)		Jitter, Peak_to_Peak _ Periodic SYSCLKP		100	ps

			ALTCORECLK[P:N]

1	tc(ALTCORCLKN)		Cycle Time _ ALTCORECLKN cycle time	3.2	25	ns

1	tc(ALTCORECLKP)		Cycle Time _ ALTCORECLKP cycle time	3.2	25	ns

3	tw(ALTCORECLKN)		Pulse Width _ ALTCORECLKN high	0.45*tc(ALTCORECLKN)	0.55*tc(ALTCORECLKN)	ns

2	tw(ALTCORECLKN)		Pulse Width _ ALTCORECLKN low	0.45*tc(ALTCORECLKN)	0.55*tc(ALTCORECLKN)	ns

2	tw(ALTCORECLKP)		Pulse Width _ ALTCORECLKP high	0.45*tc(ALTCORECLKP)	0.55*tc(ALTCORECLKP)	ns

3	tw(ALTCORECLKP)		Pulse Width _ ALTCORECLKP low	0.45*tc(ALTCORECLKP)	0.55*tc(ALTCORECLKP)	ns

4	tr(ALTCORECLKN_250mv)		Transition Time _ ALTCORECLKN Rise time	50	350	ps
			(250mV)	50	350	ps
			(250mV)

4	tf(ALTCORECLKN_250mv)		Transition Time _ ALTCORECLKN Fall time (250mV)	50	350	ps

4	tr(ALTCORECLKP_250mv)		Transition Time _ ALTCORECLKP Rise time	50	350	ps
			(250mV)	50	350	ps
			(250mV)

4	tf(ALTCORECLKP_250mv)		Transition Time _ ALTCORECLKP Fall time (250mV)	50	350	ps


Copyright 2011 Texas Instruments Incorporated						165

ADVANCE INFORMATION

	TMS320TCI6618
	Communications Infrastructure KeyStone SoC
	SPRS688—February 2011					www.ti.com
						www.ti.com
	Table 7-60		Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 2 of 3)
	(see Figure 7-29 and Figure 7-30)

	No.				Min	Max	Unit
	5	tj(ALTCORECLKN)		Jitter, Peak_to_Peak _ Periodic ALTCORECLKN		100	ps

	5	tj(ALTCORECLKP)		Jitter, Peak_to_Peak _ Periodic ALTCORECLKP		100	ps

				SRIOSGMIICLK[P:N]

	1	tc(SRIOSMGMIICLKN)		Cycle Time _ SRIOSMGMIICLKN cycle time	3.2 or 4 or 6.4		ns

	1	tc(SRIOSMGMIICLKP)		Cycle Time _ SRIOSMGMIICLKP cycle time	3.2 or 4 or 6.4		ns

	3	tw(SRIOSMGMIICLKN)		Pulse Width _ SRIOSMGMIICLKN high	0.45*tc(SRIOSGMIICLKN)	0.55*tc(SRIOSGMIICLKN)	ns

ADVANCE	2	tw(SRIOSMGMIICLKN)		Pulse Width _ SRIOSMGMIICLKN low	0.45*tc(SRIOSGMIICLKN)	0.55*tc(SRIOSGMIICLKN)	ns

	2	tw(SRIOSMGMIICLKP)		Pulse Width _ SRIOSMGMIICLKP high	50	350	ps
	2	tw(SRIOSMGMIICLKP)		Pulse Width _ SRIOSMGMIICLKP high	0.45*tc(SRIOSGMIICLKP)	0.55*tc(SRIOSGMIICLKP)	ns
	3	tw(SRIOSMGMIICLKP)		Pulse Width _ SRIOSMGMIICLKP low	0.45*tc(SRIOSGMIICLKP)	0.55*tc(SRIOSGMIICLKP)	ns
	4	tr(SRIOSMGMIICLKN_250mv)		Transition Time _ SRIOSMGMIICLKN Rise time	50	350	ps
				(250mV)
	4	tf(SRIOSMGMIICLKN_250mv)		Transition Time _ SRIOSMGMIICLKN Fall time	50	350	ps
				(250mV)	50	350	ps
				(250mV)

	4	tr(SRIOSMGMIICLKP_250mv)		Transition Time _ SRIOSMGMIICLKP Rise time
INFORMATION				(250mV)

	4	tf(SRIOSMGMIICLKP_250mv)		Transition Time _ SRIOSMGMIICLKP Fall time	50	350	ps
	4	tf(SRIOSMGMIICLKP_250mv)		Transition Time _ SRIOSMGMIICLKP Fall time
				(250mV)
				(250mV)

	5	tj(SRIOSMGMIICLKN)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN		4	ps,RMS

	5	tj(SRIOSMGMIICLKP)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP		4	ps,RMS

	5	tj(SRIOSMGMIICLKN)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKN		8	ps,RMS
				(SRIO Not Used)		8	ps,RMS
				(SRIO Not Used)

	5	tj(SRIOSMGMIICLKP)		Jitter, Peak_to_Peak _ Periodic SRIOSMGMIICLKP		8	ps,RMS
				(SRIO Not Used)		8	ps,RMS
				(SRIO Not Used)

				HyperLink CLK[P:N]

	1	tc(MCMCLKN)		Cycle Time _ MCMCLKN cycle time	3.2 or 4 or 6.4		ns

	1	tc(MCMCLKP)		Cycle Time _ MCMCLKP cycle time	3.2 or 4 or 6.4		ns

	3	tw(MCMCLKN)		Pulse Width _ MCMCLKN high	0.45*tc(MCMCLKN)	0.55*tc(MCMCLKN)	ns

	2	tw(MCMCLKN)		Pulse Width _ MCMCLKN low	0.45*tc(MCMCLKN)	0.55*tc(MCMCLKN)	ns

	2	tw(MCMCLKP)		Pulse Width _ MCMCLKP high	0.45*tc(MCMCLKP)	0.55*tc(MCMCLKP)	ns

	3	tw(MCMCLKP)		Pulse Width _ MCMCLKP low	0.45*tc(MCMCLKP)	0.55*tc(MCMCLKP)	ns

	4	tr(MCMCLKN_250mv)		Transition Time _ MCMCLKN Rise time (250 mV)	50	350	ps

	4	tf(MCMCLKN_250mv)		Transition Time _ MCMCLKN Fall time (250 mV)	50	350	ps

	4	tr(MCMCLKP_250mv)		Transition Time _ MCMCLKP Rise time (250 mV)	50	350	ps

	4	tf(MCMCLKP_250mv)		Transition Time _ MCMCLKP Fall time (250 mV)	50	350	ps

	5	tj(MCMCLKN)		Jitter, Peak_to_Peak _ Periodic MCMCLKN		4	ps,RMS

	5	tj(MCMCLKP)		Jitter, Peak_to_Peak _ Periodic MCMCLKP		4	ps,RMS

				PCIECLK[P:N]

	1	tc(PCIECLKN)		Cycle Time _ PCIECLKN cycle time	3.2 or 4 or 6.4 or 10		ns

	1	tc(PCIECLKP)		Cycle Time _ PCIECLKP cycle time	3.2 or 4 or 6.4 or 10		ns

	3	tw(PCIECLKN)		Pulse Width _ PCIECLKN high	0.45*tc(PCIECLKN)	0.55*tc(PCIECLKN)	ns

	2	tw(PCIECLKN)		Pulse Width _ PCIECLKN low	0.45*tc(PCIECLKN)	0.55*tc(PCIECLKN)	ns

	2	tw(PCIECLKP)		Pulse Width _ PCIECLKP high	0.45*tc(PCIECLKP)	0.55*tc(PCIECLKP)	ns

	3	tw(PCIECLKP)		Pulse Width _ PCIECLKP low	0.45*tc(PCIECLKP)	0.55*tc(PCIECLKP)	ns

	4	tr(PCIECLKN_250mv)		Transition Time _ PCIECLKN Rise time (250 mV)	50	350	ps

	4	tf(PCIECLKN_250mv)		Transition Time _ PCIECLKN Fall time (250 mV)	50	350	ps


	166				Copyright 2011 Texas Instruments Incorporated

						TMS320TCI6618
			Communications Infrastructure KeyStone SoC
www.ti.com						SPRS688—February 2011
www.ti.com
Table 7-60		Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1)			(Part 3 of 3)
(see Figure 7-29 and Figure 7-30)

No.				Min		Max	Unit
4	tr(PCIECLKP_250mv)		Transition Time _ PCIECLKP Rise time (250 mV)		50	350	ps

4	tf(PCIECLKP_250mv)		Transition Time _ PCIECLKP Fall time (250 mV)		50	350	ps

5	tj(PCIECLKN)		Jitter, Peak_to_Peak _ Periodic PCIECLKN			4	ps,RMS

5	tj(PCIECLKP)		Jitter, Peak_to_Peak _ Periodic PCIECLKP			4	ps,RMS

End of Table 7-60

1 If CORECLKSEL = 0, C = 1/SYSCLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency, in ns.

2 If AIF2 is being used then SYSCLK(N|P) can be programmed only to fixed values, if AIF2 is not being used then any value in the range between the min and max values can be used.

Figure 7-29 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing

2 3