Envisia HDL Modeling Reference

2

Verilog Modeling Styles

This chapter describes the impact that different Verilog modeling styles have on Ambit

BuildGates synthesis and netlist generation. In most cases, BuildGates synthesis is able to synthesize a netlist that is functionally-equivalent (according to both exhaustive simulation and formal verification) to the input HDL model. However, the exact structure of that netlist and the run-time of the tool can vary depending upon the style of the input HDL model. In addition, there exist some HDL models for which it is impractical or infeasible to synthesize functionally-equivalent hardware. The purpose of this chapter is to describe the preferred HDL modeling style for the BuildGates synthesis tool.

In addition to specific modeling styles and their impact on the synthesized netlist, a set of special comments, known as synthesis directives, are also described in this chapter. Synthesis directives provide hints to the tool, allowing it to synthesize the netlist in a preferred manner.

This chapter includes the following information:

■Modeling Combinational Logic on page 24

■Register Inferencing on page 24

■case Statements on page 27

■for Statement on page 30

■Synthesis Directives on page 31

■Verilog Preprocessor Directives on page 44

■Compiler Directives on page 44

■Command Line Options on page 47

■VPP Flag Attribute on page 47

■Verilog-Related Commands and Globals on page 47