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Table 3-4 Predefined VHDL Libraries for the common Environment, continued

The VHDL source for these packages can be found in the following directory:

ac_shell[1]> ls $env(AMBIT_VHDL_LIBS)/version/library

where version is either 1987 or 1993, and library is one of the following: ambit, std, ieee_ambit (for hdl_vhdl_environment set to standard), ieee_synergy (for hdl_vhdl_environment set to synergy), ieee_synopsys (for hdl_vhdl_environment set to synopsys), ieee (for hdl_vhdl_environment set to common) synergy, or synopsys.

Note: All other VHDL packages referred to in the design must be explicitly analyzed by the user.

Using Arithmetic Packages From Other Vendors

It is strongly recommended that you use the global hdl_vhdl_environment to setup your

VHDL environment. This is especially important since the arithmetic packages associated with the standard, synergy, common, and synopsys enviroments have been tagged with special directives that enable the tool to implement them efficiently.

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However, it may be possible that some of the VHDL designs may have references to arithmetic packages from other synthesis vendors that must be compiled into a library named

IEEE.

To make use of these additional packages, do the following:

■Redefine the library IEEE to a new directory:

ac_shell[1]> set_vhdl_library IEEE dir_name

■Analyze the std_logic_1164 package before analyzing any vendor-specific packages. The source for this package is available in the following installation directory:

ac_shell[2]> read_vhdl -library IEEE \

$env (AMBIT_VHDL_LIBS)/1993/ieee_ambit/std_logic_1164.vhdl

This results in a local version of the IEEE library with the basic package std_logic_1164 analyzed and stored in it. Note that in this example it’s assumed that you are using the VHDL‘93 version of the std_logic_1164 package. It must be pointed out that the std_logic_1164 package (shipped with the tool) must be used in this step since it is tagged with the appropriate synthesis directives.

To read in the other vendor-specific packages that are required in the IEEE library, do the following:

ac_shell[5]> read_vhdl -library IEEE package

After this step, read any VHDL entities that use these packages.

Because the local copy of the IEEE library was created using the set_vhdl_library command, the corresponding directory is preserved after exiting from ac_shell. When reentering the ac_shell environment, reuse the IEEE library created above by redefining the IEEE library (first step). The other steps are not required.

Switching between VHDL’87 / VHDL’93

BuildGates synthesis supports both 1987 and 1993 versions of VHDL. It is possible to read in VHDL designs that are modeled using different versions. It is also possible to read in VHDL designs in one version and write out the synthesized netlist in another version.

The global hdl_vhdl_read_version can be used to specify the VHDL version of files that will be analyzed using the read_vhdl command. For example:

ac_shell[1]> set_global hdl_vhdl_read_version 1987

This ensures that only VHDL files that conform to the VHDL’87 standard are parsed successfully. The default value for this global is 1993.

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For all the packages that are part of the predefined VHDL environment, both the VHDL’87 and

VHDL’93 versions are precompiled and shipped with the tool.

It should be pointed out that when the value of the global hdl_vhdl_read_version is changed, the tool resets the libraries STD, IEEE, and AMBIT to the default values for the language setting. Therefore, you will need to redefine the library IEEE to utilize other vendorspecific IEEE packages analyzed into the correct VHDL version. See Using Arithmetic Packages From Other Vendors on page 77 for more information on incorporating vendorspecific IEEE packages into the library IEEE.

It is recommended you use the same version of VHDL for reading in a given design. If your project requires a mix of VHDL versions to be read in, in most cases you should be able to analyze both sets of VHDL files with the global hdl_vhdl_read_version set to 1993. If it is absolutely essential that the different sets of files be read in with the appropriate versionspecific syntax checking, then read in the VHDL code for the 1987 version and elaborate it with do_build_generic and save out the generic ADB file. Repeat these steps for the code using the 1993 version. In a new ac_shell session, read in the generic ADB files and run do_build_generic to link the designs together. Then proceed with constraining and optimizing the design.

Reusing Previously Analyzed Entities

For large designs, it is usually desirable to analyze all the VHDL files into a library once and then reuse the analyzed entities in subsequent synthesis sessions. The global hdl_vhdl_reuse_units can be used to import VHDL entities that were analyzed previously into a library. When set to true, do_build_generic automatically synthesizes all entities that reside in any VHDL library specified using the set_vhdl_library command. The default value of hdl_vhdl_reuse_units is false.

In the example below, assume the library MYSRC has entities TOP and BOTTOM analyzed into it. If the value of hdl_vhdl_reuse_units is set to true, then do_build_generic automatically picks up these entities for synthesis.

ac_shell[1]> set_vhdl_library MYSRC ./lib ac_shell[2]> report_vhdl_library -verbose MYSRC

The report output is as follows:

ac_shell[3]> do_build_generic

INFO: Processing design ‘TOP’ <CDFG-303>.S

INFO: Processing design ‘BOTTOM’ <CDFG-303>.

However, if hdl_vhdl_reuse_units is false, then only entities that are explicitly read in using read_vhdl in the current session will be synthesized by by the tool. In the example below, even though the library MYSRC has entities analyzed into it from a previous synthesis session, they are not synthesized because the variable hdl_vhdl_reuse_units is set to false.

ac_shell[1]> set_vhdl_library MYSRC ./lib ac_shell[2]> set_global hdl_vhdl_reuse_units false ac_shell[3]> do_build_generic

The output is as follows:

Info: No designs to process. <CDFG-301>.

Modifying Case of VHDL Names

The global variable hdl_vhdl_case can be used to control the case in which VHDL names will be stored in the tool. For example:

ac_shell[1]> set_global hdl_vhdl_case lower

Possible values for the global hdl_vhdl_case are as follows:

■lower—converts all names to lower-case (Xpg is stored as xpg)

■upper—converts all names to upper-case (Xpg is stored as XPG)

■original—preserves the case used in the declaration of the object (Xpg is stored as

Xpg)

The case of VHDL names is only relevant for references to foreign modules. Examples of foreign references are Verilog modules and library cells.

If the global hdl_vhdl_case is set to original, it is recommended that you use the same case you used when defining the object when referring to foreign objects. Therefore, VHDL component and port names should be identical in case to the Verilog module definition.