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HDL Synthesis Overview

Using get_hdl_type Command

Given a specific design, the command get_hdl_type returns the language (VHDL or

Verilog) in which that specific design was represented. For example:

ac_shell> get_hdl_type TOP

yields the following output.

VHDL

Using get_hdl_file Command

Given a specific design, the command get_hdl_file returns the name of the source HDL file from which the specified design was read in. For texample:

ac_shell> get_hdl_file BOTG

yields the following output.

design.vhd

Building Generic Netlists from HDL

The command do_build_generic is used to obtain a generic hardware implementation from HDL designs. This section explains some of the useful options that are available in conjunction with this command.

Building a Specified Module

When the -module switch is used with the do_build_generic command, the subtree of hierarchy rooted at the specified module is synthesized. To determine which module will serve as the starting point for synthesis, the tool looks for an exact match of the specified module in the HDL design pool. If an exact match is not found, a case-insensitive match is executed in the HDL design pool. If a unique match is found that corresponds to a VHDL module, then that module is used as a starting point for do_build_generic. In other words, an exact name must be specified using the -module option for Verilog modules, while a case-insensitive search is used to locate a VHDL module. An error occurs if there are no matches or multiple matches found for the design specified in the -module option.

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Multiple Top-Level Designs

The command do_build_generic assumes that there is exactly one design hierarchy rooted at a unique top-level design. In cases where the design has multiple top-level designs, you need to indicate the specific subtree in the design hierarchy to synthesize.

For example, assume that there are three top-level designs in the HDL design pool:

ac_shell> get_hdl_top_level

yields the following output.

TOP1 TOP2 TOP3

One way to synthesize all three is to use the -module option with the do_build_generic command in three separate invocations of the command:

ac_shell> do_build_generic -module TOP1

ac_shell> do_build_generic -module TOP2

ac_shell> do_build_generic -module TOP3

A more automated way of accomplishing the same results is to use the foreach command in TCL:

ac_shell> foreach top [get_hdl_top_level] {

do_build_generic -module $top

}

The same functionality can be achieved by using -all option which forces do_build_generic to synthesize all disjoint trees in the design hierarchy:

ac_shell> do_build_generic -all

For multiple top-level designs, an error results if the do_build_generic command is invoked without either the -all or -module option.

Building Parameterized Designs

When the do_build_generic command is invoked, the design is automatically elaborated such that any generic values (parameters in Verilog) explicitly specified for an instantiation are propagated and the instantiated design is synthesized with the values of generics currently propagated. The following design will be used below for example purposes.

Entity BOT is

generic (L, R: natural := 1);

port (O: out bit_vector(L downto R)); end;

Architecture A of BOT is

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HDL Synthesis Overview

begin

O <= (others => ’1’); end;

Entity TOP is

port (O: out bit_vector(7 downto 0)); end;

Architecture A of TOP is begin

I8 : entity work.BOT generic map (7, 0) port map (O); end;

When the do_build_generic command is invoked for the above example design, the following modules are built: TOP and BOT_L7_R0 (derived from the the instance I8 in design TOP). The actual values (7 and 0) of the two generics (L and R) provided in instance I8 override the default values for generics in the entity definition for BOT.

While automatic elaboration works for designs that are instantiated in some higher level design, some applications may require override of the default parameter values directly from the do_build_generic command (as in elaborating top-level modules with different values of the parameters). This override is achieved using the -parameter option which specifies values to use for the indicated generics.

For example, to synthesize the design BOT with generic values L=4 and R=1:

ac_shell> do_build_generic -module BOT -parameter {{L 3} {R 2}}

yields the following output.

Info: Building generic design BOT (instantiated from the command line) with the parameter(s) L=3, R=2 <CDFG-340>.

Info: Processing design BOT_L3_R2 <CDFG-303>.

Finished processing module: BOT_L3_R2 <ALLOC-110>.

It is an error if any generic name specified using the -parameter option is not a valid generic name for that design.