Envisia HDL Modeling Reference

VHDL Modeling Style

Writing VHDL Netlists

This section describes how to write VHDL netlists.

Selecting Bit-Level Representation

When saving the VHDL file with the write_vhdl command, the netlister preserves the port types of the current entity’s ports during netlisting. This requires generation of conversion functions that transform potentially complex VHDL port types to a simpler bit-level representation. Such conversion functions are encapsulated in a package that is generated by the netlister.

All descendant module ports are always written with the equivalent bit-level representation.

For a module that did not originate as a VHDL entity, the module’s port is also written out with the equivalent bit-level representation.

Use the global variable hdl_vhdl_write_bit_type to determine the type of the bit-level representation used in VHDL netlists. The allowed values are std_logic or std_ulogic. The default value is std_logic. For example:

ac_shell[1]> set_global hdl_vhdl_write_bit_type std_ulogic

The above command maps bit ports to internal std_ulogic ports and integer ports to internal std_ulogic_vector signals.

Note: If you do not want to preserve the original VHDL port types, use the -no_wrap option to write the module with std_logic types. Refer to the write_vhdl command in the

Envisia and Ambit Command Reference for details.

Selecting Between VHDL’87 and VHDL’93

Use the global hdl_vhdl_write_version to specify the VHDL version of the netlists that are written out using the write_vhdl command. For example:

ac_shell[1]> set_global hdl_vhdl_write_version 1987

The above command ensures that the VHDL netlists that are written out conform to the VHDL’87 standard. The default value for this global is 1993.

If you write VHDL netlists in the VHDL’87 mode, care must be taken to avoid illegal names that might be generated by synthesis. When busses are bit-blasted, the individual net names are formatted as specified by the global buscomp_generator. By default, names for the nets of a bus are generated with the square brackets (b[1]). Such names are illegal in VHDL

Envisia HDL Modeling Reference

VHDL Modeling Style

’87 and can be avoided by setting the following global prior to any do_build_generic command:

ac_shell[2]> set_global buscomp_generator %s_%d

This does not apply to VHDL ’93 mode netlists, since a name such as b[1] is written out as an escaped name \b[1]\.

Referring to VHDL Packages in Netlists

Use the global variable hdl_vhdl_write_packages to specify the set of library and use clauses that must precede every module that is being written out. For example:

ac_shell[1]> set_global hdl_vhdl_write_packages\

"ieee.std_logic_1164 atl.comps1 atl.comps2"

This results in the following clauses preceding every module that is written out:

library ieee;

use ieee.std_logic_1164.all;

library atl;

use atl.comps1.all;

use atl.comps2.all;

The default value of this global is ieee.std_logic_1164.

Writing Component Declarations

Use the global variable hdl_vhdl_write_components to specify whether the netlister should write out component declarations for the technology cells that are referred to within the modules.

In the example below, if the component declarations for all the cells in the technology library clib are encapsulated in a package called components,writing component declarations for individual modules can be disabled by setting hdl_vhdl_write_components to false,and making the components package visible to all modules being written out.

ac_shell[1]> set_global hdl_vhdl_write_components false

ac_shell[2]> set_global hdl_vhdl_write_packages\

"ieee.std_logic_1164 clib.components"

The default value for this global is true.