- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •HDL Synthesis Overview
- •HDL Synthesis Flow
- •Read Technology Libraries
- •Read Design Data
- •Build Generic Design
- •Save Generic Netlist
- •Synthesizing Mixed VHDL/Verilog Designs
- •Querying the HDL Design Pool
- •Using get_hdl_top_level Command
- •Using get_hdl_hierarchy Command
- •Using get_hdl_type Command
- •Building Generic Netlists from HDL
- •Multiple Top-Level Designs
- •Building Parameterized Designs
- •Verilog Modeling Styles
- •Modeling Combinational Logic
- •Register Inferencing
- •Latch Inference
- •Flip-Flop Inference
- •case Statements
- •Incomplete case Statement
- •Complete case Statement
- •Use of casex and casez Statements
- •for Statement
- •Synthesis Directives
- •Code Selection Directives
- •Architecture Selection Directive
- •case Statement Directives
- •Module Template Directive
- •Function and Task Mapping Directives
- •Set and Reset Synthesis Directives
- •Verilog Preprocessor Directives
- •Compiler Directives
- •The ‘for Compiler Directive
- •The ‘if Compiler Directive
- •The ‘eval Compiler Directive
- •The ‘{} Compiler Directive
- •Command Line Options
- •VPP Flag Attribute
- •Verilog-Related Commands and Globals
- •VHDL Modeling Style
- •Modeling Combinational Logic
- •Register Inferencing
- •Latch Inference
- •Flip-Flop Inferencing
- •Specifying Clock Edges
- •case Statement
- •Incomplete case Statement
- •Complete case Statement
- •for loop
- •Synthesis Directives
- •Code Selection Directives
- •Architecture Selection Directive
- •case Statement Directive
- •Enumeration Encoding Directive
- •Entity Template Directive
- •Function and Procedure Mapping Directives
- •Signed Type Directive
- •Resolution Function Directives
- •Type Conversion Directives
- •Set and Reset Synthesis Directives
- •Reading VHDL Designs
- •Using Arithmetic Packages From Other Vendors
- •Switching between VHDL’87 / VHDL’93
- •Reusing Previously Analyzed Entities
- •Modifying Case of VHDL Names
- •Writing VHDL Netlists
- •Selecting Bit-Level Representation
- •Selecting Between VHDL’87 and VHDL’93
- •Referring to VHDL Packages in Netlists
- •Writing Component Declarations
- •Hierarchical VHDL Designs
- •Component Instantiations and Bindings
- •Restrictions on Entities with Multiple Architectures
- •Precedence Rules for Architecture Selection
- •VHDL-Related Commands and Globals
- •Finite State Machine Overview
- •BuildGates Synthesis and Finite State Machines
- •Extracting the State Transition Table for the FSM
- •Viewing the State Transition Table for the FSM
- •FSM Optimization Features
- •Unreachable State Removal
- •State Assignment or Re-Encoding
- •State Minimization
- •Terminal State Check
- •Verilog and VHDL FSM Directives
- •Verilog FSM Directives
- •VHDL FSM Directives
- •FSM Coding Styles
- •Using the -reachable Option
- •Avoiding a Simulation Mismatch
- •EDIF Interface
- •Reading EDIF Designs
- •Writing EDIF Designs
- •Representing Power and Ground in EDIF
- •Net Representation for Power and Ground
- •Port Representation for Power and Ground
- •Instance Representation for Power and Ground
- •Verilog Constructs
- •Fully Supported Constructs
- •Declarations
- •Operators and Expressions
- •Partially Supported Constructs
- •Ignored Constructs
- •Unsupported Constructs
- •Summary of Verilog Constructs
- •VHDL Constructs
- •Notes on Supported Constructs
Envisia HDL Modeling Reference
5
EDIF Interface
This chapter provides a brief overview of the EDIF (Electronic Data Interchange Format) interface capabilities within BuildGates synthesis. EDIF is an industry standard format for representing and exchanging such design information between various EDA tools. BuildGates synthesis supports EDIF 2.0.0.
Reading EDIF Designs
EDIF designs can be imported into the tool using the read_edif command:
ac_shell[1]> read_edif design.edif
yields the following output.
Info: Parsing of ’design.edif’ file succeeded <EDIF-700>.
Info: Netlist transformation of ’design.edif’ succeeded <EDIF-701>. Info: Setting ’TOP’ as the top of the design hierarchy <FNP-704>. Info: Setting ’TOP’ as the default top timing module <FNP-705>.
Since EDIF represents information in the form of structural netlists, there is no need to build the design using the do_build_generic command. The read_edif command parses the EDIF file and automatically populates the BuildGates synthesis netlist database. Thus, it is possible to execute any command after read_edif that is applicable to any module in the netlist, such as report_hierarchy, find or do_optimize. For example:
ac_shell[1]> read_edif design.edif ac_shell[2]> report_hierarchy
yields the following output.
|-TOP(g) ||-MIDDLE(g)
|||-BOTTOM(g)
ac_shell[3]>find -module -full
yields the following output.
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Envisia HDL Modeling Reference
EDIF Interface
BOTTOM MIDDLE TOP
However, in case unresolved blackboxes remain after reading in EDIF designs, you may need to invoke do_build_generic to link such blackboxes.
Writing EDIF Designs
The write_edif command is used to write out designs in EDIF format. Assuming that the current module is TOP which has the following hierarchical structure:
ac_shell[4]> report_hierarchy
yields the following output.
|-TOP(g) ||-MIDDLE(g)
|||-BOTTOM(g)
The following command will write out an EDIF description of all the three modules: TOP,
MIDDLE, and BOTTOM
ac_shell[5]> write_edif -hierarchical out.edif
If the -hierarchical option is not specified, EDIF is only written out for the current module, in this case TOP:
ac_shell[6]> write_edif out.edif
The module MIDDLE will be represented as a blackbox in the EDIF output.
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