Envisia HDL Modeling Reference

VHDL Modeling Style

Figure 3-5 Implementation of set and reset Synchronous Signals in a Block Logic

Reading VHDL Designs

This section describes how to read VHDL designs into BuildGates synthesis.

Defining Logical Libraries

Each logical library used in a design with the exception of the library WORK must be associated with a physical directory, using the set_vhdl_library command.

Defining a New Logical Library

To define a new logical library, use the command as follows:

ac_shell[1]> set_vhdl_library logical_library directory

The directory name must be a valid path to an existing directory. The advantage of creating a library in this manner is that the contents of the library are preserved from one synthesis run to another.

For example:

ac_shell[1]> set_vhdl_library MYLIB /home/me/vhdlibs/lib1

ac_shell[2]> read_vhdl -library MYLIB design.vhd

The above commands analyze the file design.vhd into library MYLIB.

Envisia HDL Modeling Reference

VHDL Modeling Style

Mapping the WORK Library to an Existing Logical Library

To map the WORK library to an existing logical library, use the command as follows:

ac_shell[1]> set_vhdl_library WORK library

The library name must be the name of an existing logical library. All subsequent read_vhdl commands that do NOT have an explicit -library flag, will result in the files being analyzed and stored into the last library to which WORK was mapped. For example:

ac_shell[1]> set_vhdl_library MYLIB /home/me/vhdlibs/lib1

ac_shell[2]> set_vhdl_library WORK MYLIB

The following commands are identical and will cause design.vhd to be analyzed and stored into library MYLIB:

ac_shell[3]> read_vhdl design.vhd

ac_shell[4]> read_vhdl -library MYLIB design.vhd

However, the following command analyzes and stores information from design.vhd to library ADLIB:

ac_shell[5]> read_vhdl -library ADLIB design.vhd

By default, the library WORK is mapped to the logical library TEMP. An error message is generated if two VHDL libraries are mapped to the same physical directory.

The report_vhdl_library command shows the mapping between VHDL logical libraries and the corresponding physical directory.

An error message is generated if an attempt is made to analyze a VHDL design unit into one of the standard libraries (STD, AMBIT, IEEE, SYNERGY, SYNOPSYS) without mapping the library to a new directory using the set_vhdl_library command.

Predefined VHDL Environment

Below are listed the four predefined VHDL environments which are available in BuildGates synthesis. These environments differ mainly in the choice of the arithmetic packages that can be referred to in VHDL designs.

standard Provides the arithmetic packages standardized by the IEEE. No vendor specific packages are available in this environment. This environment is the default.

synopsys Provides the arithmetic packages supported by Synopsys’ VHDL Compiler.

These packages are not approved nor standardized in IEEE (even though they are compiled into the VHDL library ’IEEE’).

Envisia HDL Modeling Reference

VHDL Modeling Style

synergy Provides the arithmetic packages supported by Cadence’s Synergy synthesis tool.

common Union of the standard and synopsys environments that can be used in the rare instance that the design refers to arithmetic packages from both these environments.

While the default environment for BuildGates synthesis is standard, the environment setting can be changed by setting the global hdl_vhdl_environment as follows:

set_global hdl_vhdl_environment {standard|synopsys|synergy|common}

Note: The set_global command must be executed before executing read_vhdl or do_build_generic and must not be changed during the design analysis.

Table 3-1 lists the VHDL libraries and packages that are available with the standard (default) environment.

Table 3-1 Predefined VHDL Libraries for the standard Environment

Table 3-2 lists the VHDL libraries and packages that are available with the synopsys environment.

Table 3-2 Predefined VHDL Libraries for the synopsys Environment

Envisia HDL Modeling Reference

VHDL Modeling Style

Table 3-2 Predefined VHDL Libraries for the synopsys Environment

Table 3-3 lists the VHDL libraries and packages that are available with the synergy environment.

Table 3-3 Predefined VHDL Libraries for the synergy Environment

Table 3-4 lists the VHDL libraries and packages that are available with the common environment.

Table 3-4 Predefined VHDL Libraries for the common Environment