Envisia™ HDL Modeling Reference
Product Version 4.0
September 2000
© 1997-2000 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America.
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Envisia HDL Modeling Reference
Preface ............................................................................................................................ |
9 |
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 |
Other Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
9 |
Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
Text Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
About the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
Using Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
Using Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
1 |
|
HDL Synthesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
HDL Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
Read Technology Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
Read Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
15 |
Build Generic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
Save Generic Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
Synthesizing Mixed VHDL/Verilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
Querying the HDL Design Pool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
Using get_hdl_top_level Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
Using get_hdl_hierarchy Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
Using get_hdl_type Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
Using get_hdl_file Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
Building Generic Netlists from HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
Building a Specified Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
Multiple Top-Level Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
Building Parameterized Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
2 |
|
Verilog Modeling Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
Modeling Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
Register Inferencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
Latch Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
Flip-Flop Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
September 2000 |
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Envisia HDL Modeling Reference
case Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
Incomplete case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
Complete case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
Use of casex and casez Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
for Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
Synthesis Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
31 |
Code Selection Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
Architecture Selection Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
case Statement Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
Module Template Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
Function and Task Mapping Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
Set and Reset Synthesis Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
Verilog Preprocessor Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
The ‘for Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
The ‘if Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
The ‘eval Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
The ‘{} Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
VPP Flag Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
Verilog-Related Commands and Globals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
3 |
|
VHDL Modeling Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
Modeling Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
Register Inferencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
Latch Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
52 |
Flip-Flop Inferencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
Specifying Clock Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
54 |
case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
56 |
Incomplete case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
56 |
Complete case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
57 |
for loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
58 |
Synthesis Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
59 |
Code Selection Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
60 |
September 2000 |
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Envisia HDL Modeling Reference
Architecture Selection Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
case Statement Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
Enumeration Encoding Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
62 |
Entity Template Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
62 |
Function and Procedure Mapping Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
63 |
Signed Type Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
63 |
Resolution Function Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
64 |
Type Conversion Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
64 |
Set and Reset Synthesis Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
65 |
Reading VHDL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
73 |
Defining Logical Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
73 |
Predefined VHDL Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
74 |
Using Arithmetic Packages From Other Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
Switching between VHDL’87 / VHDL’93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
78 |
Reusing Previously Analyzed Entities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
79 |
Modifying Case of VHDL Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
Writing VHDL Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Selecting Bit-Level Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Selecting Between VHDL’87 and VHDL’93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Referring to VHDL Packages in Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
Writing Component Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
Hierarchical VHDL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
Component Instantiations and Bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
Restrictions on Entities with Multiple Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . |
84 |
Precedence Rules for Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
VHDL-Related Commands and Globals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
4 |
|
Finite State Machine Structure and Optimization. . . . . . . . . . . . . |
89 |
Finite State Machine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
BuildGates Synthesis and Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
91 |
Extracting the State Transition Table for the FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
92 |
Viewing the State Transition Table for the FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
92 |
FSM Optimization Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
92 |
Unreachable State Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
93 |
September 2000 |
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State Assignment or Re-Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 93 |
State Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
95 |
Terminal State Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
95 |
Verilog and VHDL FSM Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
95 |
Verilog FSM Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
95 |
VHDL FSM Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
99 |
FSM Coding Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
99 |
Using the -reachable Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
100 |
Avoiding a Simulation Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
101 |
Verification of Synthesized FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
Equivalence-Checking-Based Verification Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
Simulation-Based Verification Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
106 |
5 |
|
EDIF Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
110 |
Reading EDIF Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
110 |
Writing EDIF Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
111 |
Representing Power and Ground in EDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
Net Representation for Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
Port Representation for Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
114 |
Instance Representation for Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . |
116 |
A |
|
Verilog Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
119 |
Fully Supported Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
120 |
Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
120 |
Operators and Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
120 |
September 2000 |
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|
Partially Supported Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
122 |
Ignored Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
Unsupported Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
Summary of Verilog Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
126 |
B |
|
VHDL Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
133 |
Notes on Supported Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
138 |
VHDL Predefined Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
142 |
September 2000 |
7 |
Product Version 4.0 |
Envisia HDL Modeling Reference
September 2000 |
8 |
Product Version 4.0 |
Envisia HDL Modeling Reference
Preface
This preface contains the following sections:
■About This Manual on page 9
■Other Information Sources on page 9
■Syntax Conventions on page 10
■About the Graphical User Interface on page 11
About This Manual
This manual describes the Envisia™ HDL modeling concepts. The Ambit® BuildGates® synthesis software accepts both VHDL and Verilog design modules.
Other Information Sources
For more information about Ambit BuildGates synthesis and other related products, you can consult the sources listed here.
■Ambit BuildGates Synthesis User Guide
■Envisia and Ambit Synthesis Command Reference
■Envisia Timing Analysis User Guide
■Envisia Test Synthesis User Guide
■Envisia Distributed Synthesis User Guide
■Envisia Constraint Translator Reference
Depending on the product licenses your site has purchased, you could also have these documents.
■Envisia Physically Knowledgeable Synthesis User Guide
■Envisia Datapath Synthesis User Guide
September 2000 |
9 |
Product Version 4.0 |