Envisia HDL Modeling Reference

EDIF Interface

(port o2 (direction Output))

(port o3 (direction Output))

)

......

)

The module BOTTOM has two ports SUPPLY0 and SUPPLY1 inserted through which logic 0 and logic 1 values can be supplied to the logic within the module.

Note, since the module TOP did not have any ground logic within it, no SUPPLY0 port was added to its EDIF representation.

The corresponding globals for specifying a port representation for power and ground while reading in EDIF designs are shown below.

Instance Representation for Power and Ground

An instance representation for power and ground while writing EDIF can be specified with the global:

ac_shell[16]> set_global edifout_power_and_ground_representation instance

With this setting, all power or ground are represented as instances of power and ground cells. The following globals determine the name of power and ground cells and pins and instance names to add to each module that has a power and ground driven net within it.

Envisia HDL Modeling Reference

EDIF Interface

For the Verilog example above, the following commands are used:

ac_shell[17]> set_global edifout_power_cell_name PWRC ac_shell[18]> set_global edifout_power_pin_name PWRP ac_shell[19]> set_global edifout_power_instance_name PWRI ac_shell[20]> set_global edifout_ground_cell_name GNDC ac_shell[21]> set_global edifout_ground_pin_name GNDP ac_shell[22]> set_global edifout_ground_instance_name GNDI

ac_shell[23]> write_edif -hierarchical out.edif

will produce the following EDIF output for module BOTTOM:

(library TOP

(edifLevel 0)(technology (numberDefinition)) (cell PWRC (cellType GENERIC)

(view netlist (viewType Netlist) (interface

(port PWRP (direction Output))

)

)

)

(cell GNDC (cellType GENERIC)

(view netlist (viewType Netlist)

(interface

(port GNDP (direction Output))

)

)

)

(cell BOTTOM (cellType GENERIC)

(view netlist (viewType Netlist)

(interface

(port o1 (direction Output))

(port o2 (direction Output))

)

(contents (instance PWRI

(viewRef netlist (cellRef PWRC))

)

(instance GNDI

(viewRef netlist (cellRef GNDC))

)

(net o2 (joined

Envisia HDL Modeling Reference

EDIF Interface

(portRef PWRP (instanceRef PWRI)) (portRef o2 )

)

(property default (string "logic_1"))

)

(net o1 (joined

(portRef GNDP (instanceRef GNDI)) (portRef o1 )

)

(property default (string "logic_0"))

)

.....

Two cells PWRC and GNDC with pins PWRP and GNDP, respectively have been added. Power and ground within module BOTTOM is represented as instances of these cells.

The corresponding globals for specifying a port representation for power and ground while reading in EDIF designs are shown below.