Envisia HDL Modeling Reference
Verilog Constructs
Procedural Statements
The following procedural statements are fully supported:
■begin
■end
■case
■casex
■casez
■endcase
■default
■repeat
■Named blocks
■Variable bit select on LHS of assignment
■if
■else
■else if
Partially Supported Constructs
The following constructs are supported under specific conditions. When those conditions are not met, an error is indicated.
Construct |
Constraints |
|
|
/, % |
Supported only when the right-hand operator evaluates to a |
|
constant power of 2 |
posedge, negedge |
Can only be found within the sensitivity list of an always @ |
|
construct, such as: |
|
always @(posedge clk) |
always |
Only with @(…) triggered events with combinational or clocked |
|
logic |
for |
Bounded by constant: use only “+” or “-” index variable |
September 2000 |
122 |
Product Version 4.0 |
Envisia HDL Modeling Reference
Verilog Constructs
Construct |
Constraints |
|
|
disable |
May only disable a containing task or named block |
while |
Condition expression must evaluate to a constant at each |
|
iteration |
forever |
Loop must contain a disable statement which disables a task or |
|
block containing the forever statement |
system functions |
Only $signed and $unsigned are supported |
blocking (=) and |
See below for unsupported cases. |
non-blocking (<=) |
|
assignments |
|
|
|
Below are cases in which conditional assignment restictions exist for block and non-blocking.
All conditional assignments must be either blocking or non-blocking:
if (s)
x <= a;
else
x = a;
Results in the following error.
==> ERROR: All assignments within a conditional statement should be either all blocking or all non-blocking (File /regress/ Verilog/mixed_assign.0.v, Line 8) <CDFG-463>.
Similar for bitwise assignments, all assignments should be either blocking or non-blocking:
x[0] <= a;
x[1] = b;
Results in the following error.
==> ERROR: All assignments to individual bits of register ’x’ in module ’mixtest’ should be either all blocking or all non-blocking (File /regress/ Verilog/mixed_assign.1.v, Line 9) <CDFG-238>.
September 2000 |
123 |
Product Version 4.0 |
Envisia HDL Modeling Reference
Verilog Constructs
Ignored Constructs
The following constructs are ignored when a Verilog HDL model is read. This may cause a mismatch in results between simulation of Verilog HDL model and synthesis output netlist.
Declarations
The following declarations are ignored:
scalar, vector
small, large, medium
weak1, weak0, highz0, highz1, pull0, pull1
Structural Statements
The following structural statements or some parts of structural statements are ignored:
Instance delay specification on built-in primitives
Delay specification on continuous assignments
Signal strengths on built-in primitives
Signal strengths in continuous assignments
Procedural Statements
The following procedural statements are ignored:
Intra-assignment timing controls
Procedural delays
wait
system tasks
specify,endspecify,specparam,path delays
Unsupported Constructs
The following Verilog HDL constructs are not supported for synthesis. When these constructs are encountered in a Verilog HDL model, an error message is generated.
September 2000 |
124 |
Product Version 4.0 |
Envisia HDL Modeling Reference
Verilog Constructs
Important
Your model must not contain any of these constructs.
Declarations
The following data type declarations are not supported:
triand
trior
tri1
tri0
trireg net types
time
real
event data types
Operators and expressions
The following operators are not supported:
===, !== (identity operators)
Structural Statements
The following structural statements and built-in switches are not supported:
cmos
nmos
rcmos
rnmos
pmos
rpmos (switch primitives)
rtran
tranif0
tranif1
September 2000 |
125 |
Product Version 4.0 |