Envisia HDL Modeling Reference
Verilog Constructs
rtranif0
rtranif1
pullup
pulldown
Hierarchically referenced identifiers
Procedural Statements
The following procedural statements are not supported:
initial procedural block
deassign
force
release
fork
join
table
endtable
primitive
endprimitive -> (event triggers)
assign (procedural and procedural continuous assignments)
Module Instances
The following module instances are not supported:
defparam
Summary of Verilog Constructs
Table A-2 provides a quick cross-reference of level of support for all Verilog HDL constructs.
The support is indicated as fully supported (Full), partially supported (Partial), ignored
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Verilog Constructs
(Ignored), and not supported (No). Wherever possible, the restrictions are listed to describe the partial nature of the support for each language construct.
Table A-2 Verilog Constructs
Group |
Construct |
Support |
|
|
|
Basic |
Identifiers |
Full |
|
escaped identifiers |
Full |
|
sized constants (b,o,d,h) |
Full |
|
unsized constants |
Full |
|
signed constants (s) |
Full |
|
string constants |
No |
|
real constants |
No |
|
use of z, ? in constants |
Full |
|
use of x in constants |
Full |
|
module, endmodule |
Full |
|
macromodule |
Full |
|
hierarchical references |
No |
|
//comment |
Full |
|
/*comment*/ |
Full |
|
System tasks |
Ignored |
|
System functions |
Partial |
Data types |
wire, wand, wor, tri, triand, trior |
Full |
|
tri0, tri1 |
No |
|
supply0, supply1 |
Full |
|
trireg, small, medium, large |
No |
|
reg, integer |
Full |
|
real |
No |
|
time |
No |
|
event |
No |
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Table A-2 Verilog Constructs, continued
Group |
Construct |
Support |
|
|
|
|
parameter |
Full |
|
scalared, vectored |
Ignored |
|
input, output, inout |
Full |
|
memory |
Full |
Drive Strengths |
supply0, supply1 |
Ignored |
|
strong0, strong1 |
Ignored |
|
pull0, pull1 |
Ignored |
|
large0, large1 |
Ignored |
|
weak0, weak1 |
Ignored |
|
medium0, medium1 |
Ignored |
|
small0, small1 |
Ignored |
|
highz0, highz1 |
Ignored |
Module instances |
connect port by name, order |
Full |
|
override parameter by order |
Full |
|
defparam |
No |
|
constants connected to ports |
Full |
|
unconnected ports |
Full |
|
expressions connected to ports |
Full |
|
delay on built-in gates |
Ignored |
Built-in primitives |
and, or, nand, nor, xor, xnor |
Full |
|
not, notif0, notif1 |
Full |
|
buf, bufif0, bufif1 |
Full |
|
tran |
Full |
|
tranif0, tranif1, rtran, rtranif0, rtranif1 |
No |
|
pmos, nmos, cmos, rpmos, rnmos, rcmos |
No |
|
pullup, pulldown |
No |
UDPs |
primitive, endprimitive |
No |
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Table A-2 Verilog Constructs, continued
Group |
Construct |
Support |
|
|
|
|
table, endtable |
No |
Operators and expressions |
+, - (binary and unary) |
Full |
|
/, % |
Partial |
|
* |
Full |
|
~ |
Full |
|
bitwise &, |, ^, ~^, ^~ |
Full |
|
reduction &, |, ^, ~&, ~|, ~^, ^~ |
Full |
|
!, &&, || |
Full |
|
==, !=, <, <=, >, >= |
Full |
|
===, !== |
No |
|
<<, >> |
Full |
|
{}, {n{}} |
Full |
|
?: |
Full |
|
function call |
Full |
Event control |
delay/wait (#) |
Ignored |
|
@ |
Partial |
|
event or |
Full |
|
posedge, negedge |
Partial |
|
wait |
Ignored |
|
intra-assignment event control |
Ignored |
|
event trigger (->) |
No |
Bit and part selects |
constant bit-select, part-select of vectors in |
Full |
|
cases of constant MSB and LSB specifiers |
|
|
variable bit-select on left-hand side of an |
Full |
|
assignment |
|
Continuous assignments |
net/wire declaration |
Full |
|
using assign |
Full |
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Table A-2 Verilog Constructs, continued
Group |
Construct |
Support |
|
|
|
|
use of delay |
Ignored |
Procedural blocks |
initial |
No |
|
always (exactly one @ required) |
Partial |
Procedural statements |
; |
Full |
|
begin-end |
Full |
|
if, else |
Full |
|
a.for (constant bounds, only + and - operation |
Partial |
|
on index) |
|
awhile
arepeat
aforever
case, casex, casez, endcase, default disable
fork-join task enable
Partial
Full
Partial
Full
Partial
No
Full
|
a. A loop is unrolled to a maximum count specified in hdl_max_loop limit |
|
Procedural assignments |
blocking (=) assignments |
Full |
|
non-blocking (<=) assignments |
Full |
|
procedural continuous assignments (assign) |
No |
|
deassign |
No |
|
force, release |
No |
Functions and tasks |
function, endfunction |
Full |
|
task, endtask |
Full |
Named blocks |
named block creation |
Full |
|
local variable declaration |
Full |
Specify block |
specify, endspecify |
Ignored |
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Table A-2 Verilog Constructs, continued
Group |
Construct |
Support |
|
|
|
|
specparam |
Ignored |
|
module path delays |
Ignored |
Compiler directives |
`define |
Full |
|
`resetall |
Full |
|
`ifdef, `else, `endif |
Full |
|
`include |
Full |
VPP directives |
`if |
Full |
|
`for |
Full |
|
`eval |
Full |
|
`{} |
Full |
|
|
|
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Verilog Constructs
September 2000 |
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Product Version 4.0 |