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Mux Case Directive

If the synthesis directive value includes mux, the case statement is interpreted to mean that the decoding logic for loading the value in the register is always a multiplexer instead of a priority encoder (implies full and parallel).

always @ (sel) begin

case (sel) //ambit synthesis case = mux 3’b000 : out = d1;

3’b001 : out = d2; 3’b010 : out = d3; 3’b011 : out = d4; 3’b100 : out = d5; 3’b111 : out = d6;

endcase end

Module Template Directive

When a module is written with parameter declarations for use as a template, only the instantiated, parameterized design needs to be synthesized. The template directive on a module indicates that the template module is not to be synthesized except in the context of an instantiation.

module foo(din,dout); // ambit synthesis template parameter width := 64;

input [width-1:0] din; output [width-1:0] dout;

...

endmodule;

Function and Task Mapping Directives

The map_to_module directive is intended for use in tasks and functions, and the return_port_name directive is intended for use in functions only. They should appear within the declaration of a task or function.

// ambit synthesis map_to_module module

The map_to_module directive specifies that any call to the given task or function is to be internally mapped to an instantiation of the specified module. The statements in the task or function body are therefore ignored. Arguments to the task or function are mapped positionally onto ports in the module.

// ambit synthesis return_port_name port

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The return_port_name directive is intended for use with functions only. It may only apply to a function to which the map_to_module directive is in effect. It specifies that the return value for the function call is given by the output port of the mapped-to module.

The following code maps a function to a module mod with output z:

function f;

input a;

//ambit synthesis map_to_module mod

//ambit synthesis return_port_name z f = 0;

endfunction

With this function definition, the following two statements are equivalent:

mod i1(.z(q), .a(d));

and

assign q = f(d);

Set and Reset Synthesis Directives

When the do_build_generic command infers a register from a HDL description, it also infers set and reset control of the register and defines whether these controls are synchronous or asynchronous.

Table 2-1 summarizes the condition in which the set and reset operation is inferred in Verilog from the model. This automatic detection of the set and reset operation is always in effect, even when the synthesis directives are not used. The synthesis directives notify the tool of the user’s preference to implement the set and reset operation by using the set and reset pins on the storage element components.

Figure 2-1 provides the schematic representation of the logic and shows two ways to implement synchronous set and reset logic for inferred flip-flops.

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Figure 2-1 Implementation of set and reset Control Logic

reset

(B)

(A)controls the input to the data pin of the flip-flop component using set and reset logic, so that the data value is 1 when set is active, 0 when reset is active, and driven by the data source when both set and reset are inactive (default).

(B)implements the set and reset operation by selecting the appropriate flip-flop component (cell) from the technology library and connecting the output of set and reset logic directly to the set and reset pins of the component. The data pin of the component is driven directly by the data source.

There are six synthesis directives to support the selection of set and reset logic implementation at the block level or at the signal level for each register inferred. These synthesis directives are advisory directives only. They do not force the optimizer to implement set and reset logic with one approach; they drive the selection of the component from the technology library to provide the option for the optimizer.

Note: These synthesis directives do not change the behavior of the netlist in any way. If the code is written with synchronous control on a flip-flop, and the synthesis directive specifies asynchronous selection, the resulting implementation is synchronous. A warning message is issued if the synthesis directive conflicts with the model.

Block Directives

The synthesis directive for block level set and reset signal selection are specified as follows:

//ambit synthesis set_reset asynchronous blocks = namelist

//ambit synthesis set_reset synchronous blocks = namelist

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These synthesis directives indicate that the set and reset control logic for the registers inferred from the named blocks listed, should be connected to the component asynchronous and synchronous pins respectively.

The namelist is a comma-separated list of simple block names in string form (surrounded by quotes). Hierarchical block names are not supported.

Note: These directives must be used inside a module and precede the always blocks whose names are listed. It is an error to list an undefined block name.

The following model uses the set_reset synchronous blocks synthesis directive:

module sync_block_dff(out1, out2, clk, in, set, rst) ; output out1, out2 ;

input in, set, rst, clk ; reg out1, out2 ;

// ambit synthesis set_reset synchronous blocks = “blk_1” always @(posedge clk) begin: blk_1

if (set) out1 = 1 ;

else if (rst) out1 = 0 ;

else out1 = in ; end

always @(posedge clk) begin: blk_2 if (set)

out2 = 1 ; else if (rst) out2 = 0 ;

else out2 = in ; end

endmodule

The model above shows that out1 is inferred as a D-type flip-flop with connections to the synchronous set and reset pins, out2 is inferred as a D-type flip-flop with synchronous set and reset operations controlled through combinational logic feeding the data port D

(Figure 2-2).

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Figure 2-2 Implementation of set and reset Synchronous Block Logic

When you run read_verilog and do_build_generic, you get a report as shown below.

Signal Directives

The synthesis directives for signal level set and reset signal selection is specified as follows:

//ambit synthesis set_reset asynchronous signals = siglist

//ambit synthesis set_reset synchronous signals = siglist

In Verilog, when set and reset control logic is inferred for a register, it is possible to selectively connect some of the signals directly to the set or reset pin of the component and let the other signals propagate through logic onto the data pin.

The siglist is a comma-separated list of signal names (surrounded by quotes) in a module. Hierarchical signal names are not permitted.

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Note: These directives must be used inside a module and precede all always blocks. It is an error to list an undefined or an unused signal. Also, the signal directive must be specified in the same declarative region as the signal being attributed. An error occurs if you specify these directives for a non-existent or unused signal.

Consider the following Verilog model of using the set and reset synchronous signals synthesis directive:

module sync_sig_dff(out1, out2, clk, in, set1, set2, rst1, rst2) ; output out1, out2 ;

input in, clk, set1, set2, rst1, rst2 ; reg out1, out2 ;

//ambit synthesis set_reset synchronous signals=“set1, set2” always @(posedge clk) begin

if (set1) out1 = 1 ;

else if (rst1) out1 = 0 ; else out1 = in ;

end

always @(posedge clk) begin if (set2)

out2 = 1 ; else if (rst2) out2 = 0 ; else out2 = in ;

end endmodule

The flip-flop inferred for out1 and out2 are connected so that the set signal connects to the synchronous set pin and the reset signal is connected through combinational logic feeding the data port D. Figure 2-3 shows the generated logic.

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Figure 2-3 Implementation of set and reset Synchronous Signal Logic

When you run read_verilog and do_build_generic, you get a report as shown below.

Signals in a Block Directive

For Verilog, both the block and the signal name can be specified for the set and reset operation by using the following directives:

//ambit synthesis set_reset asynchronous block(name)=siglist

//ambit synthesis set_reset synchronous block(name)=siglist

Only the listed signals in the named block that perform synchronous or asynchronous set and reset operation are connected to the synchronous or asynchronous pins respectively.

For registers inferred from other blocks, these signals are connected to the data input.

Consider the following model using the set_reset synchronous signals in a block synthesis directive:

module sync_block_sig_dff(out1, out2, clk, in, rst) ;

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output out1, out2 ; input in, clk, rst ; reg out1, out2 ;

/* ambit synthesis set_reset synchronous block(blk_1) = “rst” */ always @(posedge clk) begin:blk_1

if (rst) out1 = 0;

else out1 = in ; end

always @(posedge clk) begin:blk_2 if (rst)

out2 = 0; else out2 = in ; end

endmodule

Figure 2-4 shows the generated logic. Notice that the reset control (rst signal) for the out1 flip-flop is connected directly to the synchronous reset pin, whereas the reset control for the out2 flip-flop is connected through logic to the data input pin. This is because only the rst signal in blk_1 was identified in the directive.

Figure 2-4 Implementation of set and reset Synchronous Signals in a Block Logic