Envisia HDL Modeling Reference

Verilog Modeling Styles

A latch is inferred because not all of the possible case expressions are covered in the case statement (not full); the case expression 4’b0000 is not covered in the case statement

(see Assigning a Default Value for Incomplete case Statements on page 28 to avoid latches).

Furthermore one or more case items overlap (not parallel) and a priority encoder is required to implement the equivalent hardware.

In the following model, a casex statement is used with don’t care conditions in the same manner as the casez statement (above). The main difference between the two models is that the casex statement below masks three bits of the select line that would match x, z, or ?, but the casez statement above will not mask x in the select line.

module casex_example( sel, out); input [3:0] sel;

output [1:0] out; reg [1:0] out; always @(sel) begin

casex (sel)

4’bxxx1 : out = 2’b00; 4’bxx1x : out = 2’b01; 4’bx1xx : out = 2’b10; 4’b1xxx : out = 2’b11; default : out = 2’bxx;

endcase

end

endmodule

When you run read_verilog and do_build_generic, you get a report of the casez statement as shown below.

ac_shell[4]> read_verilog casex.v

ac_shell[5]> do_build_generic

for Statement

The for statement is used for describing repetitive operations. For example, all the bits of a vector (in) can be stored in reverse order using a for statement.