Envisia HDL Modeling Reference

EDIF Interface

Representing Power and Ground in EDIF

When writing out an EDIF netlist, the power and ground can be represented as nets, ports, or instances. The global edifout_power_and_ground_representation is used to select the one of these three representations. Each of these styles is described in the following Verilog example.

module TOP (o1, o2, o3); output o1, o2, o3; BOTTOM i0 (o1, o2); assign o3 = 1’b1;

endmodule

module BOTTOM (o1, o2); output o1, o2; assign o1 = 1’b0; assign o2 = 1’b1;

endmodule

Net Representation for Power and Ground

A net representation for power and ground while writing EDIF can be specified with the global as follows:

ac_shell[7]> set_global edifout_power_and_ground_representation net

With this setting, the following globals determine the name of power nets and the property name and value associated with it.

Any net driven by logic 1 will be named according to the global edifout_power_net_name.

If this global is not set, the power nets will retain the same name as in the netlist database.

All power nets will have a property whose name and value are determined by the globals edifout_power_net_property_name and edifout_power_net_property_value.

For example, the following commands:

Envisia HDL Modeling Reference

EDIF Interface

ac_shell[8]> set_global edifout_power_net_name POWER

ac_shell[9]> set_global edifout_power_net_property_name SUPPLY

ac_shell[10]> set_global edifout_power_net_property_value LOGIC1

ac_shell[11]> write_edif -hierarchical out.edif

will produce the following output for module BOTTOM.

.....

(library TOP

(edifLevel 0)(technology (numberDefinition)) (cell BOTTOM (cellType GENERIC)

(view netlist (viewType Netlist) (interface

(port o1 (direction Output))

(port o2 (direction Output))

)

(contents (net o1 (joined

(portRef o1 )

)

(property default (string "logic_0"))

)

(net POWER

(joined

(portRef o2 )

)

(property SUPPLY (string "LOGIC1"))

)

)

)

)

.....

Since port o2 is driven to logic 1, the corresponding power net has been named POWER and the appropriate property attached to it.

The corresponding globals for naming ground nets are shown below.

Envisia HDL Modeling Reference

EDIF Interface

edifout_ground_net_property_name default

edifout_ground_net_property_value logic_0

In the EDIF output above, since we did not specify any values for the above three ground related globals, the ground net o1 retains its original name and has the default property attached to it.

Below are the corresponding globals for specifying power and ground nets while reading in

EDIF designs.

Port Representation for Power and Ground

A port representation for power and ground while writing out EDIF can be specified with the global as follows:

ac_shell[12]> set_global edifout_power_and_ground_representation port

With this setting, power or ground in all modules will be represented as ports of the module. The following globals determine the name of power and ground ports that will be added to each module that has a power or ground driven net within it.

Envisia HDL Modeling Reference

EDIF Interface

Any net driven by logic 1 will be represented with the value of the global edifout_power_port_name. Any net driven by logic 0 will be represented with the value of the global edifout_ground_port_name.

For the Verilog example above, the following commands:

ac_shell[13]> set_global edifout_power_port_name SUPPLY1

ac_shell[14]> set_global edifout_ground_port_name SUPPLY0

ac_shell[15]> write_edif -hierarchical out.edif

will produce the following EDIF output:

(cell BOTTOM (cellType GENERIC)

(view netlist (viewType Netlist)

(interface

(port SUPPLY0 (direction Input))

(port SUPPLY1 (direction Input))

(port o1 (direction Output))

(port o2 (direction Output))

)

(contents (net o2 (joined

(portRef SUPPLY1) (portRef o2 )

)

(property default (string "logic_1"))

)

(net o1 (joined

(portRef SUPPLY0) (portRef o1 )

)

(property default (string "logic_0"))

)

)

)

)

(cell TOP (cellType GENERIC)

(view netlist (viewType Netlist)

(interface

(port SUPPLY1 (direction Input))

(port o1 (direction Output))