Envisia HDL Modeling Reference
B
VHDL Constructs
This appendix lists the VHDL constructs supported by the BuildGates synthesis tool and
VHDL and shows the category to which each belongs (see Table B-1). The list is subject to change and modifications are ongoing. Both VHDL 1987 and VHDL 1993 style descriptions are supported. The constructs are classified by one of the following four categories:
■Synthesized fully (Full)
■Synthesized partially or in specific contexts (Partial)
■Construct is ignored and a warning is generated (Ignored)
■Construct is unsupported and an error message is generated (No)
Table B-1 VHDL Constructs Supported in Ambit BuildGates Synthesis
Construct |
|
|
Support |
|
|
|
|
Design Entity & |
Entity Declaration |
Entity header |
Full |
Configuration |
|
Entity declarative part |
Full |
|
|
||
|
|
Entity statement part |
Ignored |
|
Architecture Body |
Architecture |
Full |
|
|
declarative part |
|
|
|
Architecture statement |
Full |
|
|
part |
|
|
Configuration |
Configuration |
Partial |
|
Declaration |
declarative part |
|
|
|
Block configuration |
Full |
|
|
Component |
Full |
|
|
configuration |
|
|
|
|
|
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VHDL Constructs
Table B-1 VHDL Constructs Supported in Ambit BuildGates Synthesis, continued
Construct |
|
|
Support |
|
|
|
|
Subprogram & |
Subprogram |
|
Full |
Packages |
Declaration |
|
|
|
Subprogram Body |
Subprogram |
Full |
|
|
declarative part |
|
|
|
Subprogram |
Full |
|
|
statement part |
|
|
Subprogram |
|
Full |
|
Overloading |
|
|
|
Resolution Function |
|
Partial |
|
Package |
Package declarative |
Full |
|
Declaration |
part |
|
|
|
Deferred constants |
Full |
|
Package Body |
|
Full |
Types |
Scalar Type |
Enumeration type |
Full |
|
Definition |
Integer |
Full |
|
|
||
|
|
Physical |
Ignored |
|
|
Floating |
Ignored |
|
Composite Type |
Array |
Full |
|
Definition |
Record |
Full |
|
|
||
|
Access Type |
|
Ignored |
|
Definition |
|
|
|
File Type Definition |
|
Ignored |
|
|
|
|
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Table B-1 VHDL Constructs Supported in Ambit BuildGates Synthesis, continued
Construct |
|
|
Support |
|
|
|
|
Declarations |
Subprogram |
|
Full |
|
Declaration |
|
|
|
Subprogram Body |
|
Full |
|
Type Declaration |
|
Full |
|
Subtype |
|
Full |
|
Declaration |
|
|
|
Object Declaration |
Constant |
Full |
|
|
Signal |
Full |
|
|
Variable |
Full |
|
|
Shared variable |
No |
|
|
File |
No |
|
Alias Declaration |
|
Full |
|
Attribute |
|
Full |
|
Declaration |
|
|
|
Component |
|
Full |
|
Declaration |
|
|
|
Group Template |
|
No |
|
Declaration |
|
|
|
Group Declaration |
|
No |
Specifications |
Attribute |
|
Full |
|
Specification |
|
|
|
Configuration |
|
Full |
|
Specification |
|
|
|
Disconnection |
|
No |
|
Specification |
|
|
|
|
|
|
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VHDL Constructs
Table B-1 VHDL Constructs Supported in Ambit BuildGates Synthesis, continued
Construct |
|
|
Support |
|
|
|
|
Expressions |
Logical Operators |
and, or, nand, nor, xor, |
Full |
|
|
xnor |
|
|
Relational |
=, /=, >, <, >=, <= |
Full |
|
Operators |
|
|
|
Shift Operators |
sll, srl, sra |
Full |
|
|
sla, ror, rol |
Partial |
|
Arithmetic |
+, -, & |
Full |
|
Operators |
|
|
Sign Operators
Multiplying
Operators
Miscellaneous
Operators
Operands
Aggregates
Function calls
+, - |
Full |
* |
Full |
/, mod, rem |
Partial |
* * |
Partial |
abs |
Full |
not |
Full |
Integer literal |
Full |
Real Literal |
Ignore |
Physical Literal |
Ignore |
Enumeration Literal |
Full |
String Literal |
Full |
Bit String Literal |
Full |
Null Literal |
No |
Record Aggregates |
Full |
Array Aggregates |
Full |
Qualified Expression |
Full |
Type Conversion |
Full |
Allocators |
No |
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VHDL Constructs
Table B-1 VHDL Constructs Supported in Ambit BuildGates Synthesis, continued
Construct |
|
|
Support |
|
|
|
|
Statements |
Sequential |
|
|
|
Statements |
|
|
|
Wait |
Sensitivity clause |
Partial |
|
|
Condition clause |
Partial |
|
|
Timeout clause |
Ignored |
|
Assertion |
|
Ignored |
|
Report |
|
Ignored |
|
Signal Assignment |
|
Full |
|
Variable |
|
Full |
|
Assignment |
|
|
|
Procedure Call |
|
Full |
|
If |
|
Full |
|
Case |
|
Full |
|
Loop |
Unconditional Loop |
No |
|
|
While Loop |
Partial |
|
|
For Loop |
Full |
|
Next |
|
Full |
|
Exit |
|
Full |
|
Return |
|
Full |
|
Null |
|
Full |
|
Concurrent |
|
|
|
Statements |
|
|
|
|
|
|
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