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Verilog Modeling Styles

Only single-bit controls are accepted for set and reset. See Synthesis Directives on page 31 for more information on controlling the set and reset connections for a flip-flop.

case Statements

Using a case statement allows for multi-way branching in a functional description. When a case statement is used as a decoder to assign one of several different values to a variable, the logic can be implemented as combinational or sequential logic based on whether the variable is assigned a value in branches of the case statement. Ambit BuildGates synthesis automatically determines whether a case statement is full and/or parallel. A case statement is full if all possible case items are specified. A case statement is parallel if none of the case items overlap. If automatic determination of full and/or parallel case is not possible, the full and parallel case directives can be used (see Full Case Directive on page 34, Parallel Case Directive on page 35).

The following sections describe the impact on synthesis for different use models and types of case statements.

■Incomplete case Statement on page 27

■Complete case Statement on page 28

■Use of casex and casez Statements on page 28

Incomplete case Statement

When a case statement specifies only some of the values that the case expression can possibly have, a latch is inferred. For example, a state transition table may be modeled as follows:

reg [2:0] curr_state, next_state, modifier; always @ (modifier)

case (curr_state)

3’b000 : next_state = 3’b100 & modifier ; 3’b001 : next_state = 3’b110 | modifier ; 3’b010 : next_state = 3’b001 & modifier ; 3’b100 : next_state = 3’b101 | modifier ; 3’b101 : next_state = 3’b010 & modifier ; 3’b110 : next_state = 3’b000 | modifier ;

endcase

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Verilog Modeling Styles

The next_state variable is assigned a new value if curr_state is any one of the six values specified. For the other two possible states, the next_state variable retains its previous value. This behavior causes the software to infer a 3-bit latch for next_state.

Complete case Statement

If you do not want to infer a latch, the next_state variable must be assigned a value under all situations. In other words, the next_state variable should have a default value.

Assigning a Default Value for Incomplete case Statements

There are several ways to assign a default value to next_state.

■The first approach model follows:

next_state = 3’b000 ; // unconditional assignment

case (curr_state)

…

endcase

The next_state variable is assigned a value unconditionally, then it is modified appropriately by the case statement. This approach prevents the software from inferring

a latch.

■The second approach model follows:

case (curr_state)

…

default : next_state = 3’b000 ; // all other cases endcase

Use the default case in the case statement to capture all the remaining cases where the next_state variable is assigned a value. This approach also prevents the software from inferring a latch.

■The third approach model uses the full case synthesis directive as discussed in Full Case Directive on page 34. This states that the simulation results between functional and gate level models may mismatch if this synthesis directive is used.

Use of casex and casez Statements

The casex and casez statements allow the x, z and ? values to be treated like don’t care conditions when comparing for the matching case. These statements are treated like case statements with the following differences:

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Verilog Modeling Styles

■casez statement allows z and ? to be treated as a don’t care condition

■casex statement allows x, z and ? to be treated as a don’t care condition

The following model shows a casez statement using don’t care conditions to mask three of the four bits in the decoding select line (input sel).

module casez_example(sel, out); input [3:0] sel;

output [1:0] out; reg [1:0] out; always @ (sel) begin

casez (sel)

4’b???1 : out = 2’b00; 4’b??1? : out = 2’b01; 4’b?1?? : out = 2’b10; 4’b1??? : out = 2’b11;

endcase

end

endmodule

In the example out will be set to 2’b00 if sel[0] = 1, regardless of the values of sel[3], sel[2] and sel[1]; out will be set to 2’b01 only if sel[0] = 0 and sel[1] = 1, regardless of the values of sel[3] and se[2].

If you perform technology independent mapping, running read_verilog and do_build_generic provides you with a report of the casez statement as shown below.

ac_shell[1]> read_verilog casez.v

ac_shell[2]> do_build_generic