Envisia HDL Modeling Reference

Preface

■Envisia Low Power Synthesis User Guide

BuildGates synthesis is often used with other Cadence® tools during various design flows.

The following documents provide information about these tools and flows. Availability of these documents depends on the product licenses your site has purchased.

■Cadence Timing Library Format Reference

■Cadence Pearl Timing Analyzer User Guide

■Cadence General Constraint Format Reference

The following books are helpful references.

■IEEE 1364 Verilog HDL LRM

■TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-Wesley Publishing Company

Syntax Conventions

This section provides the Text Command Syntax used in this document.

Text Command Syntax

The list below describes the syntax conventions used for the Ambit BuildGates synthesis text interface commands.

Important

Command names and arguments are case sensitive. User-defined information is case sensitive for Verilog designs and, depending on the value specified for the global variable hdl_vhdl_case, may be case sensitive as well.